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參數(shù)資料
| 型號： | SI3000PPT-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR SI3000 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 已用 IC / 零件： | SI3000 |
| 已供物品： | 主板和子卡組套 |
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Si3000
Rev. 1.4
31
7. 16-Pin SOIC Land Pattern
Figure illustrates the recommended land pattern for the Si3000 16-pin SOIC. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 20. 16-Pin SOIC Land Pattern Diagram
Table 16. 16-Pin MSOP Land Pattern Dimensions
Dimension
Feature
mm
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and Tolerancing per ASME Y14.5M-1994.
3.
This Land Pattern Design is based on the IPC-7351 guidelines.
4.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
5.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m
minimum, all the way around the pad.
Stencil Design
6.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
7.
The stencil thickness should be 0.125 mm (5 mils).
8.
The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9.
A No-Clean, Type-3 solder paste is recommended.
10.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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