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參數(shù)資料
| 型號(hào)： | SG3525AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | PULSE WIDTH MODULATOR CONTROL CIRCUITS |
| 中文描述： | 0.5 A SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 205K |
| 代理商： | SG3525AN |
SG3525A SG3527A
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS
(VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Output Voltage (TJ = +25
°
C)
Line Regulation (+8.0 V
≤
VCC
≤
+35 V)
Load Regulation (0 mA
≤
IL
≤
20 mA)
Temperature Stability
Vref
Regline
Regload
Vref/
T
Vref
5.00
5.10
5.20
Vdc
–
10
20
mV
–
20
50
mV
–
20
–
mV
Total Output Variation
Includes Line and Load Regulation over Temperature
4.95
–
5.25
Vdc
Short Circuit Current
(Vref = 0 V, TJ = +25
°
C)
ISC
–
80
100
mA
Output Noise Voltage (10 Hz
≤
f
≤
10 kHz, TJ = +25
°
C)
Long Term Stability (TJ = +125
°
C) (Note 5)
Vn
S
–
40
200
μ
Vrms
mV/khr
–
20
50
OSCILLATOR SECTION
(Note 6, unless otherwise noted.)
Initial Accuracy (TJ = +25
°
C)
Frequency Stability with Voltage
(+8.0 V
≤
VCC
≤
+35 V)
–
±
2.0
±
6.0
%
fosc
DVCC
–
±
1.0
±
2.0
%
Frequency Stability with Temperature
fosc
D
T
–
±
0.3
–
%
Minimum Frequency (RT = 150 k
, CT = 0.2
μ
F)
Maximum Frequency (RT = 2.0 k
, CT = 1.0 nF)
Current Mirror (IRT = 2.0 mA)
Clock Amplitude
fmin
fmax
–
50
–
Hz
400
–
–
kHz
1.7
2.0
2.2
mA
3.0
3.5
–
V
Clock Width (TJ = +25
°
C)
Sync Threshold
0.3
0.5
1.0
μ
s
1.2
2.0
2.8
V
Sync Input Current (Sync Voltage = +3.5 V)
–
1.0
2.5
mA
ERROR AMPLIFIER SECTION
(VCM = +5.1 V)
Input Offset Voltage
VIO
IIB
IIO
AVOL
VOL
VOH
CMRR
–
2.0
10
mV
Input Bias Current
–
1.0
10
μ
A
Input Offset Current
–
–
1.0
μ
A
DC Open Loop Gain (RL
≥
10 M
)
Low Level Output Voltage
60
75
–
dB
–
0.2
0.5
V
High Level Output Voltage
3.8
5.6
–
V
Common Mode Rejection Ratio (+1.5 V
≤
VCM
≤
+5.2 V)
Power Supply Rejection Ratio (+8.0 V
≤
VCC
≤
+35 V)
60
75
–
dB
PSRR
50
60
–
dB
PWM COMPARATOR SECTION
Minimum Duty Cycle
DCmin
DCmax
Vth
Vth
IIB
–
–
0
%
Maximum Duty Cycle
45
49
–
%
Input Threshold, Zero Duty Cycle (Note 6)
0.6
0.9
–
V
Input Threshold, Maximum Duty Cycle (Note 6)
–
3.3
3.6
V
Input Bias Current
–
0.05
1.0
μ
A
NOTES:
4.Tlow = 0
°
for SG3525A, 3527A
5.Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability
from lot to lot.
6.Tested at fosc = 40 kHz (RT = 3.6 k
, CT = 0.01
μ
F, RD = 0
).
Thigh = +70
°
C for SG3525A, 3527A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SG3527AN | PULSE WIDTH MODULATOR CONTROL CIRCUITS |
| SG3527A | REGULATING PULSE WIDTH MODULATOR |
| SG3527ADW | REGULATING PULSE WIDTH MODULATOR |
| SG3527AJ | REGULATING PULSE WIDTH MODULATOR |
| SG3527AN | REGULATING PULSE WIDTH MODULATOR |
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