參數(shù)資料
型號: SG3527AJ
廠商: MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP
元件分類: 穩(wěn)壓器
英文描述: REGULATING PULSE WIDTH MODULATOR
中文描述: 0.5 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, CDIP16
封裝: HERMETIC SEALED, CERAMIC, DIP-16
文件頁數(shù): 1/8頁
文件大小: 205K
代理商: SG3527AJ
SEMICONDUCTOR
TECHNICAL DATA
PULSE WIDTH MODULATOR
CONTROL CIRCUITS
PIN CONNECTIONS
Order this document by SG3525A/D
N SUFFIX
PLASTIC PACKAGE
CASE 648
16
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16L)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top View)
Inv. Input
Sync
OSC. Output
RT
Discharge
Soft–Start
Noninv. Input
CT
Compensation
Shutdown
Output A
VC
Output B
VCC
Vref
Ground
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
SG3525AN
SG3525ADW
TA = 0
°
to +70
°
C
Plastic DIP
SO–16L
SG3527AN
Plastic DIP
16
1
1
MOTOROLA ANALOG IC DEVICE DATA
The SG3525A, SG3527A pulse width modulator control circuits offer
improved performance and lower external parts count when implemented for
controlling all types of switching power supplies. The on–chip +5.1 V
reference is trimmed to
±
1% and the error amplifier has an input
common–mode voltage range that includes the reference voltage, thus
eliminating the need for external divider resistors. A sync input to the
oscillator enables multiple units to be slaved or a single unit to be
synchronized to an external system clock. A wide range of deadtime can be
programmed by a single resistor connected between the CT and Discharge
pins. These devices also feature built–in soft–start circuitry, requiring only an
external timing capacitor. A shutdown pin controls both the soft–start circuitry
and the output stages, providing instantaneous turn off through the PWM
latch with pulsed shutdown, as well as soft–start recycle with longer
shutdown commands. The under voltage lockout inhibits the outputs and the
changing of the soft–start capacitor when VCC is below nominal. The output
stages are totem–pole design capable of sinking and sourcing in excess of
200 mA. The output stage of the SG3525A features NOR logic resulting in a
low output for an off–state while the SG3527A utilized OR logic which gives a
high output when off.
8.0 V to 35 V Operation
5.1 V
±
1.0% Trimmed Reference
100 Hz to 400 kHz Oscillator Range
Separate Oscillator Sync Pin
Adjustable Deadtime Control
Input Undervoltage Lockout
Latching PWM to Prevent Multiple Pulses
Pulse–by–Pulse Shutdown
Dual Source/Sink Outputs:
±
400 mA Peak
Representative Block Diagram
NOR
NOR
16
15
12
4
3
6
5
7
9
1
2
8
10
Reference
Regulator
Under–
Voltage
Lockout
Oscillator
Latch
F/F
Q
Q
– PWM
Error
Amp
+
+
To Internal
Circuitry
VREF
Vref
VCC
Ground
OSC Output
Sync
RT
CT
Discharge
Compensation
INV. Input
Noninv. Input
CSoft–Start
Shutdown
5.0k
S
R
S
50
μ
A
VC
13
Output A
11
14
Output B
SG3525A Output Stage
13
VC
Output A
11
Output B
14
SG3527A
Output Stage
OR
OR
5.0k
Motorola, Inc. 1996
Rev 2
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