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參數(shù)資料
| 型號： | SFC05-5.WMT |
| 元件分類： | TVS二極管 - 瞬態(tài)電壓抑制 |
| 英文描述： | 200 W, UNIDIRECTIONAL, 5 ELEMENT, SILICON, TVS DIODE, MO-211BB |
| 封裝： | LEAD FREE, FLIP CHIP, MO-211, CSP-6 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 212K |
| 代理商： | SFC05-5.WMT |
5
2004 Semtech Corp.
www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC05-5
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coat-
ings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving ad-
equate solder volume without compromising assembly
yields. A 0.100mm thick, laser cut, electro-polished
stencil with 0.275mm square apertures and rounded
corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using the reflow
requirements for IPC/JEDEC standard J-STD-020 for
assembly of small body components. During reflow,
the component will self-align itself on the pad.
Circuit Board Layout Recommendations for Suppres-
sion of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Stencil Design
Applications Information (Continued)
Assembly Guideline for Pb-Free Soldering
The following are recommendations for the assembly
of this device:
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