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| 型號(hào)： | SE370C736AFZT |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁(yè)數(shù)： | 13/48頁(yè) |
| 文件大小： | 711K |
| 代理商： | SE370C736AFZT |
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TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupts (continued)
chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
The TMS370Cx36 has 21 hardware system interrupts (plus RESET) as shown in Table 7. Each system interrupt
has a dedicated vector located in program memory through which control is passed to the interrupt service
routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are individually
maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit
is individually readable for software polling or for determining which interrupt source generated the associated
system interrupt.
Twenty of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is
supported. Software configuration of the external interrupts is performed through the INT1 control register in
peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or
falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable
or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual-
or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should
be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupt
INT1 can be software configured as a general-purpose input pin if the interrupt function is not required.
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