參數資料
型號： SE370C710FZS
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁數： 40/48頁
文件大?。?/td> 711K
代理商： SE370C710FZS
TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external clocking requirements for clock divided by 4 (see Note 9 and Figure 16)
NO.
PARAMETER
MIN
MAX
UNIT
1
tw(Cl)
tr(Cl)
tf(CI)
td(CIH-SCL)
CLKIN
Pulse duration, XTAL2/CLKIN (see Note 10)
20
ns
2
Rise time, XTAL2/CLKIN
30
ns
3
Fall time, XTAL2/CLKIN
30
ns
4
Delay time, XTAL2/CLKIN rise to SYSCLK fall
100
ns
Crystal operating frequency
Internal system clock operating frequency
2
20
MHz
SYSCLK
0.5
5
MHz
SYSCLK = CLKIN/4
NOTES:
9. For VIL and VIH, refer to recommended operating conditions.
10. This pulse may be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an
XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
3
2
1
4
SYSCLK
Figure 16. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL) (see Note 9 and Figure 17)
NO.
1
PARAMETER
MIN
20
MAX
UNIT
ns
tw(Cl)
tr(Cl)
tf(CI)
td(CIH-SCH)
CLKIN
Pulse duration, XTAL2/CLKIN (see Note 10)
2
Rise time, XTAL2/CLKIN
30
ns
3
Fall time, XTAL2/CLKIN
30
ns
4
Delay time, XTAL2/CLKIN rise to SYSCLK rise
100
ns
Crystal operating frequency
Internal system clock operating frequency
2
5
MHz
SYSCLK
2
5
MHz
SYSCLK = CLKIN/1
NOTES:
9. For VIL and VIH, refer to recommended operating conditions.
10. This pulse can be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an
XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
4
3
2
1
XTAL2/CLKIN
SYSCLK
Figure 17. External Clock Timing for Divide-by-1
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