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參數(shù)資料
| 型號： | SE370C710FZS |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 711K |
| 代理商： | SE370C710FZS |
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TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupts
The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 5. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of
the ST.
GROUP 2
CPU
NMI
Logic
Enable
IE1
IE2
Level 1 INT
Level 2 INT
PACT 3 PRI
Priority
Cmd/Def Entry 7
Cmd/Def Entry 6
Cmd/Def Entry 5
Cmd/Def Entry 4
Cmd/Def Entry 3
Cmd/Def Entry 2
AD INT
AD PRI
ADC1
STATUS REG
EXT INT1
INT1 PRI
INT1
SPI INT
SPI PRI
SPI
Cmd/Def Entry 1
Cmd/Def Entry 0
GROUP 3
PACT 1 PRI
Overflow
CP1 Edge
CP2 Edge
CP3 Edge
CP4 Edge
CP5 Edge
CP6 Edge
Circular Buffer
GROUP 1
PACT 2 PRI
SCI TXINT
SCI RXINT
PACT
Default Timer
Figure 5. Interrupt Control
Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is selectively configured on either the high- or
low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
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