參數(shù)資料
型號(hào)： SDA5250
廠商： SIEMENS A G
元件分類： 圖文
英文描述： ICs for Consumer Electronics
中文描述： TELETEXT AND VPS/PDC DECODER, PQCC84
文件頁數(shù)： 71/143頁
文件大?。?/td> 1050K
代理商： SDA5250
SDA 525x
Semiconductor Group
71
1998-04-08
If two requests of different priority levels are received simultaneously, the request of
higher priority level will be serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines which request is serviced. Thus
within each priority level there is a second priority structure determined by the polling
sequence, see in
Table 18
.
Note that the “priority within level” structure is only used to resolve simultaneous
requests of the same priority level.
6.3.4.1
The process whereby a higher-level interrupt request interrupts a lower-level interrupt
service program is called nesting. In this case the address of the next instruction in the
lower-priority service program is pushed onto the stack, the stack pointer is incremented
by two and processor control is transferred to the program memory location of the first
instruction of the higher-level service program. The last instruction of the higher-priority
interrupt service program must be a RETI-instruction. This instruction clears the higher
“priority-level-active” flip-flop. RETI also returns processor control to the next instruction
of the lower-level interrupt service program. Since the lower “priority-level-active” flip-
flop has remained set, higher priority interrupts are re-enabled while further lower-priority
interrupts remain disabled.
Interrupt Nesting
Table 18
Source
1.
2.
3.
4.
5.
6.
Priority within Level
(highest)
IE0
TF0
IE1
TF1
RI/TI
DVIRST
DHIRST
EVENST
LIN24ST
AVIRST
AHIRST
IADC
7.
(lowest)
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