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參數(shù)資料
| 型號： | SDA2546-5 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface |
| 中文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 153K |
| 代理商： | SDA2546-5 |
Semiconductor Group
30
SDA 2546-5
Control Functions of the
I
2
C Bus
The device is controlled by the controller (master) via
I
2
C Bus in two operating modes: real cycle,
and reprogramming cycle, including erase and write to a memory address. In both operating modes,
the controller, as transmitter, has to provide 3 bytes to the bus after the start condition. Each byte
has to be followed by an acknowledge bit. During a memory read, at least eight additional clock
pulses are required to accept the data from the memory, before the stop condition may follow. In the
programming case, the active programming process is only started by the stop condition after data
input,
see figure 3
.
The chip select word includes the chip select bit CS. Thus is possible to parallel two memory
devices. Chip select is obtained when the control bits logically correspond to the condition selected
at the select input CS. The most significant bits A8 and A9 are inputs with the chip select words
CS/E.
Checking the End of the Programming Cycle and Breaking off the Programming Cycle
Addressing the chip by the input of CS/E during active reprogramming terminates the programming
cycle. If the chip is addressed by entering CS/A, this will be ignored. Only when the programming
cycle has terminated will the chip react on CS/A. With this procedure the end of the programming
cycle can be checked,
see figure 3
.
Memory Read
After the input of the two control words CS/E and WA, the resetting of the start condition and the
input of a third control word CS/A, the memory is set ready to read. During acknowledge clock
no. 9, the memory information is transferred in parallel to the internal data register. Subsequent to
the falling edge of the acknowledge clock, the data output is low-impedance and the first data bit can
be sampled,
see figure 4
.
With each shift clock, an additional bit reaches the output. After reading a byte, the internal address
counter is automatically incremented through the master receiver acknowledge, so that any number
of memory locations can be read one after the other. At address 512, an overflow to address 0 is not
initiated. With the stop condition, the data output returns to high-impedance mode. The internal
sequence control of the memory component is reset from the read to the quiescent with the stop
condition.
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