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參數(shù)資料
| 型號： | SDA2546-5 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface |
| 中文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 153K |
| 代理商： | SDA2546-5 |
Semiconductor Group
38
SDA 2546-5
Timing Conditions
Parameter
Symbol
Limit Values
Unit
min.
max.
Minimum time the bus must be free
before a new transmission can start
t
BUF
t
HD; STA
t
LOW
t
HIGH
4.7
μ
s
μ
s
μ
s
μ
s
Start condition hold time
4.0
Clock low period
4.7
Clock high period
4.0
Start condition set-up time,
only valid for repeated start code
t
SU; STA
t
SU; DAT
t
R
t
F
t
SU; SPO
4.7
μ
s
ns
μ
s
ns
μ
s
Data set-up time
250
Rise time of both the SDA- and SCL-line
1
Fall time of both the SDA- and SCL-line
300
Stop condition set-up time
4.7
Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of
the falling edge of SCL. All values refer to
V
IH
and
V
IL
level.
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