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參數(shù)資料
| 型號(hào)： | sda 9400 |
| 廠商： | SIEMENS AG |
| 英文描述： | Single-Chip Picture in Picture IC(單芯片畫中畫IC) |
| 中文描述： | 單片集成電路畫中畫（單芯片畫中畫集成電路） |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大小： | 121K |
| 代理商： | SDA 9400 |
Published by Semiconductor Group
Siemens Aktiengesellschaft
Ordering No. B110-H7217-X-X-7600
Printed in Germany
PS 05983.
1102980029
Availability
The SDA 9400 and a complete
documentation is available
in samples 1998. Mass
production is scheduled for
1999. A dedicated
engineering support team is
there to assist you. Also an
application board is available.
Please contact your local
Siemens office for further
How to reach us:
http://www.siemens.de/semiconductor/
address/address.htm
Siemens AG 1998.
All Rights Reserved.
Please note that any information contained in this
publication may be subject to change. Siemens
reserves the right to make changes to or to
discontinue any product or service identified in
this publication without notice.
Please contact our regional offices to receive the
latest version of the relevant information to verify,
before placing orders, that the information being
relied upon is current.
Technical Data
I
2
C Bus control (400 kHz)
P-MQFP-64 package
3.3 V ± 5% supply voltage
0.35μm CMOS technology
4:2:2 processing
B
YUVIN
8
CVBS
Analog
colour
decoder
+
RGB
input
SDA
9206
ABACUS
SDA
9400
SCARA-
BAEUS
SDA
9280
Display-
processor
PIP
processor
e.g.
SDA 9488
SDA
936X
Deflection
controller
CVBS
HIN1
VIN1
Y
8
UV
8
HOUT, VOUT,
HREF
Y
U
V
SYNC
R
G
H-Drive
V-Drive
E/W
Y
U
V
CLK1=27MHz
CLKOUT
Embedded memory
– 5 Mbit embedded DRAM
core for field memories
– 192 kbit embedded DRAM
core for line memories
The SDA 9400 contains allnecessary
functional blocks on a single chip:
Flexible input sync controller
Input format conversion
Low data rate processing
Memory controller
Flexible output sync controller
Output format conversion
High data rate processing
I
2
C Bus interface
PLL for frequency doubling
and in a leading edge technology
5.2 Mbit embedded DRAM for line
and field memories.
VLDR
Horizontal
decimation
Noise
reduction and
measurement
Motion
detector
and phase
detection
ED
eDRAM
Interfaces
Data buffer
Voltage control
Test controller
OFC
output
format
conversion
HDR
Scan rate
conversion
Vertical
interpolation
IFC
Input
format
conversion
MMC
Controller
OSC
Output sync
controller
ISC
Input sync
controller
PLL 1
Clock doubling
LM
Line memory
LM
Line memory
PLL 2
Clock
doubling
I
2
C
I
2
C Bus
Interface
Wien
S
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Shanghai 200003
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Halfway House1685
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A
AUS
B
BR
CDN
CH
D
DK
E
F
FIN
IND
GB
GR
HK
I
IRL
J
N
NL
NZ
P
PL
RC
ROK
RUS
S
SGP
TR
ZA
USA
VRC
MAL
PK
The SDA 9400 is a single core IC for 100 Hz containing all necessary blocks
Block Diagram SDA 9400
Application of a 100 Hz TV set
Application Example
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