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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | SCF5250AG120 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/56闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MPU COLDFIRE 120MHZ 144-QFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 300 |
| 绯诲垪锛� | SCF52xx |
| 鏍稿績铏曠悊鍣細 | Coldfire V2 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 120MHz |
| 閫ｉ€氭€э細 | EBI/EMI锛孖²C锛孖DE锛孧MC锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孖²S锛孭OR锛屼覆琛岄煶闋�锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| RAM 瀹归噺锛� | 128K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.08 V ~ 1.32 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 6x12b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -20°C ~ 70°C |
| 灏佽/澶栨锛� | 144-LQFP |
| 鍖呰锛� | 鎵樼洡 |
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
18
Freescale Semiconductor
3.15
Queued Serial Peripheral Interface (QSPI)
The QSPI interface is a high-speed serial interface allowing transmit and receive of serial data. Pin
descriptions are given in Table 11.
3.16
Crystal Trim
The XTRIM/GPIO0 output produces a pulse-density modulated phase/frequency difference signal to be
used after low-pass filtering to control varicap-voltage to control crystal oscillation frequency. This will
lock the crystal to the incoming digital audio signal.
3.17
Clock Out
The MCLK1/GPIO11 and QSPI_CS2/MCLK2/GPIO24 can serve as DAC clock outputs. When
programmed as DAC clock outputs, these signals are directly derived from the crystal oscillator or clock
Input (CRIN).
DDATAO/CTS1/SDATA0_SDIO1/GPIO1 Secure Digital serial data bit 0
Memory Stick interface 1 data I/O
SCL0/SDATA1_BS1/GPIO41
Secure Digital serial data bit 1
Memory Stick interface 1 strobe
DDATA1/RTS1/SDATA2_BS2/GPIO2
Secure Digital serial data bit 2
Memory Stick interface 2 strobe
Reset output signal
Selection between Reset function and SDATA2_BS2 is done by programming PLLCR
register.
SDA0/SDATA3/GPIO42
Secure Digital serial data bit 3
Table 11. Queued Serial Peripheral Interface (QSPI) Signals
Serial Module Signal
Description
QSPICLK/SUBR/GPIO25
Multiplexed signal IIC interface clock or QSPI clock output Function select is done via
PLLCR register.
RCK/QSPIDIN/QSPI_DOUT/GPIO26
Multiplexed signal IIC interface data or QSPI data input. Function select is done via
PLLCR register.
RCK/QSPI_DIN/QSPI_DOUT/GPIO26
QSPI_DOUT/SFSY/GPIO27
QSPI data output.
QSPICS0/EBUIN4GPIO15
4 different QSPI chip selects.
QSPICS1/EBUOUT2/GPIO16
QSPICS2/MCLK2/GPIO24
CS1/QSPICS3/GPIO28
Table 10. Flash Memory Card Signals (continued)
Flash Memory Signal
Description
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VI-BTX-IX-B1 | CONVERTER MOD DC/DC 5.2V 75W |
| VI-BTX-IW-B1 | CONVERTER MOD DC/DC 5.2V 100W |
| MC9S12B64MFUE | IC MCU 64K FLASH 25MHZ 80-QFP |
| VI-BTW-IX-B1 | CONVERTER MOD DC/DC 5.5V 75W |
| MCF5212LCVM66J | IC MCU 256K FLASH 66MHZ 81MAPBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| SCF5250CAG120 | 鍔熻兘鎻忚堪:IC MPU COLDFIRE 120MHZ 144-QFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:SCF52xx 妯�(bi膩o)婧�(zh菙n)鍖呰:330 绯诲垪:- 鏍稿績铏曠悊鍣�:- 鑺珨灏哄:8/16-浣� 閫熷害:40MHz 閫ｉ€氭€�:UART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孭WM锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):32 绋嬪簭瀛樺劜鍣ㄥ閲�:- 绋嬪簭瀛樺劜鍣ㄩ鍨�:澶栭儴绋嬪簭瀛樺劜鍣� EEPROM 澶у皬:- RAM 瀹归噺:- 闆诲 - 闆绘簮 (Vcc/Vdd):4.5 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:- 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:100-BQFP 鍖呰:绠′欢 |
| SCF5250CPV120 | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:SCF5250 Integrated ColdFire Microprocessor |
| SCF5250DAG120 | 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:AMADEUS PLUS - Bulk |
| SCF5250LAG100 | 鍔熻兘鎻忚堪:IC MPU COLDFIRE 100MHZ 144-LQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:SCF52xx 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:260 绯诲垪:73S12xx 鏍稿績铏曠悊鍣�:80515 鑺珨灏哄:8-浣� 閫熷害:24MHz 閫ｉ€氭€�:I²C锛屾櫤鑳藉崱锛孶ART/USART锛孶SB 澶栧湇瑷�(sh猫)鍌�:LED锛孭OR锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):9 绋嬪簭瀛樺劜鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:2K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2.7 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:- 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:68-VFQFN 瑁搁湶鐒婄洡 鍖呰:绠′欢 |
| SCF5250LPV100 | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
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