參數(shù)資料
型號(hào): SCF5250AG120
廠商: Motorola, Inc.
英文描述: SCF5250 Integrated ColdFire Microprocessor
中文描述: SCF5250提供了集成的ColdFire微處理器
文件頁(yè)數(shù): 20/48頁(yè)
文件大小: 767K
代理商: SCF5250AG120
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Signal Descriptions
Freescale Semiconductor
20
4.19.4 Debug Data
The debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,
DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displays
captured processor data and break-point status.
4.19.5 Processor Status
The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and
PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is
synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.
Table 13
shows the encodings of these signals.
.
Table 13. Processor Status Signal Encodings
PST[3:0]
Definition
(HEX)
(BINARY)
$0
0000
Continue execution
$1
0001
Begin execution of an instruction
$2
0010
Reserved
$3
0011
Entry into user-mode
$4
0100
Begin execution of PULSE and WDDATA instructions
$5
0101
Begin execution of taken branch or Synch_PC
1
$6
0110
Reserved
$7
0111
Begin execution of RTE instruction
$8
1000
Begin 1-byte data transfer on DDATA
$9
1001
Begin 2-byte data transfer on DDATA
$A
1010
Begin 3-byte data transfer on DDATA
$B
1011
Begin 4-byte data transfer on DDATA
$C
1100
Exception processing
2
$D
1101
Emulator mode entry exception processing
2
$E
1110
Processor is stopped, waiting for interrupt
2
$F
1111
Processor is halted
2
Rev. B enhancement.
These encodings are asserted for multiple cycles.
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