參數(shù)資料
型號(hào)： SCANPSC110F
廠商： National Semiconductor Corporation
英文描述： SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port(掃描橋分層多點(diǎn)可設(shè)定地址的JTAG端口)
中文描述： 掃描橋?qū)哟魏投帱c(diǎn)尋址JTAG端口（掃描橋分層多點(diǎn)可設(shè)定地址的的JTAG端口）
文件頁數(shù)： 16/29頁
文件大?。?/td> 459K
代理商： SCANPSC110F
Special Features
BIST SUPPORT
The sequence of instructions to run BIST testing on a parked
SCANPSC110F Bridge port is as follows:
1.
Pre-load the Boundary register of the device under test if
needed.
2.
Initialize the TCK counter to 00000000 Hex. Note that
the TCK counter is initialized to 00000000 Hex upon
Test-Logic-Reset so this step may not be necessary.
3.
Issue the CNTRON instruction to the ’PSC110F, to en-
able the TCK counter.
4.
Shift the PARKRTIinstruction into the ’PSC110F instruc-
tion register and BISTinstruction into the instruction reg-
ister of the device under test.
5.
Issue the CNTRSEL instruction to the ’PSC110F.
6.
Load the TCK counter (Shift the 32-bit value represent-
ing the number of TCK
cycles needed to execute the
BIST operation into the TCK counter register).
7.
Bit 7 of the Mode register can be scanned to check the
status of the TCK counter, (MODESEL instruction fol-
lowed by a Shift-DR ). Bit 7 logic “0” means the counter
has not reached terminal count, logic “1” means that the
counter has reached terminal count and the BIST opera-
tion has completed.
8.
Execute the CNTROFF instruction.
9.
Unpark the LSP and scan out the result of the BIST op-
eration (the CNTROFF instruction must be executed be-
fore unparking the LSP).
The Self test will begin on the rising edge of TCK
B
following
the Update-DR TAP controller state.
RESET
Reset operations can be performed at three levels. The high-
est level resets all ’PSC110F registers and all of the local
scan chains of selected and unselected ’PSC110Fs. This
“Level 1” reset is performed whenever the ’PSC110F TAP
Controller
enters
the
Test-Logic-Reset can be entered synchronously by forcing
TMS
high for at least five (5) TCK
pulses, or asynchro-
nously by asserting the TRST pin. A “Level 1” reset forces all
’PSC110Fs into the Wait-For-Address state, parks all local
scan chains in the Test-Logic-Reset state, and initializes all
’PSC110F registers.
Test-Logic-Reset
state.
TABLE 10. Reset Configurations for Registers
Register
MCGR
Instruction
Mode
LFSR
32-Bit Counter
Bit Width
2
8
8
16
32
Initial Hex Value
0
AA (IDCODE Instruction)
01
0000
00000000
The SOFTRESET instruction is provided to perform a “Level
2” reset of all LSP’s of selected ’PSC110Fs. SOFTRESET
forces all TMS
signals high, placing the corresponding local
TAP Controllers in the Test-Logic-Reset state within five (5)
TCK
B
cycles.
The third level of reset is the resetting of individual local
ports. An individual LSP can be reset by parking the port in
the Test-Logic-Reset state via the PARKTLR instruction. To
reset an individual LSP that is parked in one of the other
parked states, the LSP must first be unparked via the UN-
PARK instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of the
four TAP Controller states: Test-Logic-Reset, Run-Test/Idle,
Pause-DR, or Pause-IR. The ’PSC110F is able to park a lo-
cal chain by controlling the local Test Mode Select outputs
(TMS
) (see Figure 4 ). TMS
is forced high for parking
in the Test-Logic-Reset state, and forced low for parking in
Run-Test/Idle, Pause-IR, or Pause-DR states. Local chain
access is achieved by issuing the UNPARK instruction. The
LSPs do not become unparked until the ’PSC110F TAP Con-
troller is sequenced through a specified synchronization
state. Synchronization occurs in the Run-Test/Idle state for
LSPs parked in Test-Logic-Resetor Run-Test/Idle;and in the
Pause-DR or Pause-IR state for ports parked in Pause-DR
or Pause-IR, respectively.
Figures 11, 12 show the waveforms for synchronization of a
local chain that was parked in the Test-Logic-Reset state.
Once the UNPARK instruction is received in the instruction
register, the LSPC forces TMS
L
low on the falling edge of
TCK
B
.
This moves the local chain TAP Controllers to the synchroni-
zation state (Run-Test/Idle) where they stay until synchroni-
zation occurs. If the next state of the ’PSC110F TAP Control-
ler is Run-Test/Idle TMS
is connected to TMS
and the
local TAP Controllers are synchronized to the ’PSC110F TAP
Controller as shown in Figure 12 If the next state after
DS100327-15
FIGURE 11. Local Scan Port Synchronization on Second Pass
S
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