參數(shù)資料
型號: SCAN921025HSM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST
中文描述: LINE DRIVER, PBGA49
封裝: BGA-49
文件頁數(shù): 8/21頁
文件大小: 527K
代理商: SCAN921025HSM
Deserializer Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t
HZR
Parameter
Conditions
Figure 14
Pin/Freq.
Rout(0-9)
Min
Typ
Max
Units
HIGH to TRI-STATE
Delay
LOW to TRI-STATE
Delay
TRI-STATE to HIGH
Delay
TRI-STATE to LOW
Delay
Deserializer PLL Lock
Time from PWRDWN
(with SYNCPAT)
Deserializer PLL Lock
time from SYNCPAT
2.8
10
ns
t
LZR
2.8
10
ns
t
ZHR
4.2
10
ns
t
ZLR
4.2
10
ns
t
DSR1
Figure 15
Figure 16
(Note 7)
20MHz
1.7
3.5
μs
80MHz
1.0
2.5
μs
t
DSR2
20MHz
80MHz
0.65
0.29
1.5
0.8
μs
μs
t
ZHLK
TRI-STATE to HIGH
Delay (power-up)
t
RNMI-R
Ideal Noise Margin
Right
Figure 20
LOCK
3.7
12
ns
VCC = 3.15 to 3.6V
VCC = 3.0V
80MHz
+335
+215
+1
ps
20MHz
ns
t
RNMI-L
Ideal Noise Margin Left
Figure 20
VCC = 3.15 to 3.6V
VCC = 3.0V
80MHz
-395
-520
-1
ps
20MHz
ns
SCAN Circuitry Timing Requirements
Symbol
f
MAX
Parameter
Conditions
Min
25.0
Typ
50.0
Max
Units
MHz
Maximum TCK Clock
Frequency
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to
TCK
R
L
= 500
, C
L
= 35 pF
t
S
t
H
t
S
t
H
t
W
t
W
t
REC
1.0
2.0
2.5
1.5
10.0
2.5
2.0
ns
ns
ns
ns
ns
ns
ns
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,
VOD,
VTH and VTL which are differential voltages.
Note 4:
t
LLHT
and t
LHLT
specifications are Guaranteed By Design (GBD) using statistical analysis.
Note 5:
Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 6:
t
DJIT
specifications are Guaranteed By Design using statistical analysis.
Note 7:
For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and with specific
conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either t
DSR1
timing or t
DSR2
timing. t
DSR1
is the
time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. t
DSR2
is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from
not receiving data to receiving synchronization patterns (SYNCPATs).
Note 8:
t
RNM
is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
Margin is Guaranteed By Design (GBD) using statistical analysis.
S
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