參數(shù)資料
型號: SCAN12100
廠商: National Semiconductor Corporation
英文描述: 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement
中文描述: 1228.8和614.4 Mbps的CPRI串行解串器與自動重新同步和高精度延遲校準測量
文件頁數(shù): 4/14頁
文件大?。?/td> 217K
代理商: SCAN12100
Pin #
79
Pin Name
CDET
I/O, Type
O, LVTTL or 1.8V
LVCMOS
Description
Comma Detect.
0 = no comma yet detected in the incoming serial stream or receiver PLL not locked.
1 = the receiver PLL is locked and a positive or negative comma bit sequence detected
in the incoming bit stream. The serial to parallel converter is aligned to the proper 10-
bit word boundary when comma alignment is enabled (CALIGN_EN = 1).
CONTROL PINS
82
81
PE [0]
PE [1]
I, LVTTL or 1.8V
LVCMOS Internal
pull down
Transmitter de-emphasis configuration.
Pulling both pins low enables MDIO control, default is no de-emphasis.
PE1
PE0
0
0
0
1
1
0
1
1
Receive input equalization configuration.
Pulling both pins low enables MDIO control, default is no receive equalization.
EQ1
EQ0
0
0
No receive equalization
0
1
Low receive equalization
1
0
Medium receive equalization
1
1
Maximum receive equalization
Power down control signals.
TXPWDNB
0 = Transmitter is powered down and DOUT± pins are high impedance.
1 = Transmitter is powered up.
RXPWDNB
0 = Receiver is powered down and ROUT [9:0] as well as LOS, LOCKB, CDET,
RXCLK, and SYSCLK are high impedance.
1 = Receiver is powered up.
Comma alignment enable.
0 = comma alignment circuitry disabled. Receiver will not realign 10-bit data based on
incoming comma characters. CDET pin still flags comma detection.
1 = comma detect and alignment circuitry enabled. Receiver aligns 10-bit data to
incoming comma character and flags comma detect through CDET pin.
Receiver recovered clock mode
0 = Write mode. RXCLK pin is a recovered clock output.
(RXCLK = output pin)
1 = Read mode. RXCLK pin is ROUT [9:0] bus read input strobe.
(RXCLK = input pin)
Selects whether single-ended data and control pins are 3.3V LVTTL or 1.8V LVCMOS.
0 = 1.8V LVCMOS. Tie VSEL to ground and power IOVDD at 1.8 V.
1 = 3.3V LVTTL. Tie VSEL to IOVDD supply and power IOVDD at 3.3 V.
Selects SerDes mode.
0 = Base station mode
1 = Reserved for future use
Hardware SerDes reset. Resets PLLs and MDIO registers.
0 = Hardware SerDes reset
1 = Normal operation
No de-emphasis
Low de-emphasis
Medium de-emphasis
Maximum de-emphasis
88
89
EQ [0]
EQ [1]
I, LVTTL or 1.8V
LVCMOS Internal
pull down
90
91
TXPWDNB
RXPWDNB
I, LVTTL or 1.8V
LVCMOS Internal
pull down
92
CALIGN_EN
I, LVTTL or 1.8V
LVCMOS Internal
pull down
93
RXCLKMODE
I, LVTTL or 1.8V
LVCMOS Internal
pull down
80
VSEL
I, LVTTL or 1.8V
LVCMOS Internal
pull down
I, LVTTL or 1.8V
LVCMOS Internal
pull down
94
OPMODE
95
RESETB
I, LVTTL or 1.8V
LVCMOS Internal
pull down
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參數(shù)描述
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