參數(shù)資料
型號: SCAN12100
廠商: National Semiconductor Corporation
英文描述: 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement
中文描述: 1228.8和614.4 Mbps的CPRI串行解串器與自動重新同步和高精度延遲校準測量
文件頁數(shù): 10/14頁
文件大小: 217K
代理商: SCAN12100
Symbol
Parameter
Condition
Min
Typ
(Note 2)
Max
Units
t
H-MDIO
Hold Time
MDC rising edge to MDIO (input)
invalid
MDIO (output) delay from MDC
rising edge
Measured at MDIO when used as
output, CL = 470 pF
10
ns
t
D-MDIO
Delay Time
0
300
ns
t
X-MDIO
Transition Time
1
ns
MINIMUM PULSE WIDTH, Hardware Reset
(Note 11)
t
TX-RST
Transmiter Reset
t
RX-RST
Receiver Reset
t
RST
SerDes Reset
JTAG TIMING SPECIFICATIONS
f
JTAG
JTAG TCK Frequency
t
R-J
t
F-J
80%)
t
S-TDI
Setup Time TDI to TCK High or Low
t
H-TDI
Hold Time TDI to TCK High or Low
t
S-TMS
Setup Time TMS to TCK High or
Low
t
H-TMS
Hold Time TMS to TCK High or Low
t
W-TCK
TCK Pulse Width
t
W-TRST
TRSTB Pulse Width
t
REC
Recovery Time TRSTB to TCK
DELAY CALIBRATION MEASUREMENT (DCM)
(Notes 10, 12, 13)
T
14
T
14
Delay Accuracy
T
offset
T
offset
Delay Accuracy
T
ser
Serializer Delay Accuracy
T
des
Deserializer Delay Accuracy
T
in-out
T
in-out
Delay Accuracy
T
out-in
T
out-in
Delay Accuracy
TXPWDNB = 0
1
us
RXPWDNB = 0
1
us
RESETB = 0
1
us
R
L
= 1000
, C
L
= 15 pF
25
MHz
TDO data transition time (20% to
2
ns
2
ns
2
ns
2
ns
2
ns
10
ns
2.5
ns
14
ns
Receive and Transmit PLLs locked
to valid hyperframe data.
± 800
ps
± 800
ps
± 1200
ps
± 1200
ps
± 1200
ps
± 1200
ps
Note 1:
“Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2:
Typical parameters are measured at nominal supply levels and T
A
= 25°C. They are for reference purposes and are not production-tested.
Note 3:
Transmit Jitter testing methodology is defined in Appendix 48B of IEEE 802.2ae-2002. The SCAN12100 transmit output jitter is constant for all valid CPRI
datarates. The transmit jitter is significantly less than the specified limits in terms of UI.
Note 4:
CJPAT is a stress pattern defined in IEEE 802.2ae-2002 Appendix 48A
Note 5:
CDET nominal valid duration is determined by the CPRI data rate. CDET timing is similar to the ROUT[0:9] timing.
Note 6:
Transmit or Receive K28.5 pattern. Assumes TXCLK is stable and toggles only after all SerDes clocks become synchronous.
Note 7:
Transmit latency is fixed once the link is established and is guaranteed by the Tser specification.
Note 8:
Receive latency is fixed once the link is established and is guaranteed by the Tdes specification.
Note 9:
Receiver output timing specifications for TS-R and TH-R are tested at the CPRI rate of 1.2288 Gbps.
Note 10:
Limits are guaranteed by design and characterization over process, supply voltage, and temperature variations.
Note 11:
Limits are guaranteed by design.
Note 12:
Serial side DCM readings are referenced to the first bit of the K28.5 pattern {110000 0101 001111 1010}. Parallel side DCM readings are referenced
to the TXCLK or RXCLK edge (not the data edge) that registers the K character as an input or output.
Note 13:
DCM readings are valid when the RXCLK pin on the SCAN12100 is used as an output in "WRITE" mode (RXCLKMODE = 0) and IOVDD = 3.3V.
Note 14:
Edge rate characterization includes the loading effects of 1.0 uF AC-coupling capacitors and 4 inches of 100 ohm differential microstrip.
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