參數(shù)資料
型號(hào): SC9RS08KA1J3CDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO6
封裝: 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, DFN-6
文件頁(yè)數(shù): 103/134頁(yè)
文件大?。?/td> 3114K
代理商: SC9RS08KA1J3CDB
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Chapter 8 Central Processor Unit (RS08CPUV1)
SC9RS08KA2 Series Data Sheet, Rev. 1
70
Freescale Semiconductor
BSR rel
Branch Subroutine
PC
← (PC) + 2
Push PC to shadow PC
PC
← (PC) + rel
—— REL
AD
rr
3
CBEQA #opr8i,rel
CBEQ opr8a,rel
CBEQ ,X,rel (1),(2)
CBEQ X,rel (1)
Compare and Branch if
Equal
PC
← (PC) + $0003 + rel, if (A) – (M) = $00
PC
← (PC) + $0003 + rel, if (A) – (M) = $00
PC
← (PC) + $0003 + rel, if (A) – (X) = $00
——
IMM
DIR
IX
DIR
41
31
ii
rr
dd rr
0E rr
0F rr
4
5
CLC
Clear Carry Bit
C
← 0
—0
INH
38
1
CLR opr8a
CLR opr5a
CLR ,X (1)
CLRA
CLRX (1)
Clear
M
← $00
A
← $00
X
← $00
1—
DIR
SRT
IX
INH
3F
8x / 9x
8E
4F
8F
dd
3
2
1
2
CMP #opr8i
CMP opr8a
CMP ,X (1)
CMP X (1)
Compare Accumulator
with Memory
(A) – (M)
(A) – (X)
IMM
DIR
IX
INH
A1
B1
ii
dd
0E
0F
2
3
COMA
Complement
(One’s Complement)
A
← (A)
1INH
43
1
DBNZ opr8a,rel
DBNZ ,X,rel (1)
DBNZA rel
DBNZX rel (1)
Decrement and Branch if
Not Zero
A
←(A)–$01orM ←(M)-$01
PC
← (PC) + $0003 + rel if (result) ≠ 0 for DBNZ
direct
PC
← (PC) + $0002 + rel if (result) ≠ 0 for
DBNZA
X
←(X)–$01
PC
← (PC) + $0003 + rel if (result) ≠ 0
——
DIR
IX
INH
3B
4B
3B
dd rr
0E rr
rr
0F rr
7
4
7
DEC opr8a
DEC opr4a
DEC ,X (1)
DECA
DEC X
Decrement
M
← (M) – $01
A
← (A) – $01
X
← (X) – $01
DIR
TNY
IX
INH
DIR
3A
5x
5E
4A
5F
dd
5
4
1
4
EOR #opr8i
EOR opr8a
EOR ,X (1)
EOR X
Exclusive OR
Memory with
Accumulator
A
← (A ⊕ M)
A
← (A ⊕ X)
IMM
DIR
IX
DIR
A8
B8
ii
dd
0E
0F
2
3
INC opr8a
INC opr4a
INC ,X (1)
INCA
INCX (1)
Increment
M
← (M) + $01
A
← (A) + $01
X
← (X) + $01
DIR
TNY
IX
INH
3C
2x
2E
4C
2F
dd
5
4
1
4
JMP opr16a
Jump
PC
← Effective Address
— — EXT
BC
hh ll
4
JSR opr16a
Jump to Subroutine
PC
← (PC) + 3
Push PC to shadow PC
PC
← Effective Address
— — EXT
BD
hh ll
4
LDA #opr8i
LDA opr8a
LDA opr5a
LDA ,X (1)
Load Accumulator from
Memory
A
← (M)
IMM
DIR
SRT
IX
A6
B6
Cx/Dx
CE
ii
dd
2
3
Table 8-1. Instruction Set Summary (Sheet 4 of 6)
Source
Form
Description
Operation
Effect
on
CCR
Ad
dr
ess
Mode
Op
co
de
Operand
Cyc
les
ZC
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
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