參數(shù)資料
型號(hào)： SC80C32XXX-36SV
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40
封裝： 0.600 INCH, SIDE BRAZED, DIP-40
文件頁數(shù)： 78/109頁
文件大小： 10824K
代理商： SC80C32XXX-36SV
56
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Table 10-9. Overriding Signals for Alternate Functions in PB[1:0]
Note:
When TWI is enabled the slew rate control and spike filter are activate on PB1. This is not illustrated in Figure 10-6 on
page 48. The spike filter is connected between AIOxn and the TWI.
10.4
Register Description
10.4.1 PORTCR – Port Control Register
Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 1 – BBMB: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port B. The intermediate tri-state cycle is then
inserted when writing DDRBn to make an output. For further information, see “Break-Before-Make Switching” on page
Bit 0 – BBMA: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port A. The intermediate tri-state cycle is then
inserted when writing DDRAn to make an output. For further information, see “Break-Before-Make Switching” on page
Signal
PB1/OC1A/SDA/MOSI/PCINT9
PB0/T0/CLKI/PCINT8
PUOE
0
EXT_CLOCK (1)
1.
EXT_CLOCK = external clock is selected as system clock.
PUOV
0
DDOE
(SPE MSTR) + TWEN
EXT_CLOCK (1)
DDOV
TWEN SDA_OUT
0
PVOE
TWEN + (SPE MSTR) + OC1A_ENABLE
PVOV
TWEN SPE MSTR SPI_MASTER_OUT + TWEN
(SPE + MSTR) OC1A
0
PTOE
0
DIEOE
PCINT9 PCIE1
EXT_CLOCK(1) + (PCINT8 PCIE1)
DIEOV
PCINT9 PCIE1
( EXT_CLOCK(1) PWR_DOWN ) +
(EXT_CLOCK(1) PCINT8 PCIE1)
DI
PCINT9 / SPI Slave Input
CLOCK / PCINT8 / T0 Input
AIO
SDA Input
Bit
7
6
5
4
3
2
1
0
–
BBMB
BBMA
PORTCR
Read/Write
R
R/W
Initial Value
0
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