- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25623 > SC80C32XXX-36SV (ATMEL CORP) 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 PDF資料下載
參數(shù)資料
| 型號： | SC80C32XXX-36SV |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, SIDE BRAZED, DIP-40 |
| 文件頁數(shù)： | 42/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | SC80C32XXX-36SV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁
286
7593L–AVR–09/12
AT90USB64/128
USB host controller state after an hardware reset is ‘Reset’. When the USB controller is enabled
and the USB Host controller is selected, the USB controller is in ‘Idle’ state. In this state, the
USB Host controller waits for the Device connection, with a minimum power consumption.
The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to
enter in ‘Host Ready’ state.
The Host controller enters in Suspend state when the USB bus is in Suspend state, that is, when
the Host controller doesn’t generate the Start of Frame. In this state, the USB consumption is
minimum. The Host controller exits to the Suspend state when starting to generate the SOF over
the USB line.
24.4
Device detection
A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In
other words, when the USB Host Controller detects the Device pull-up on the D+ line. To enable
this detection, the Host Controller has to provide the Vbus power supply to the Device.
The Device Disconnection is detected by the USB Host controller when the USB Idle correspond
to D+ and D- low on the USB line.
24.5
Pipe selection
Prior to any operation performed by the CPU, the Pipe must first be selected. This is done by
setting PNUM2:0 bits (UPNUM register) with the Pipe number which will be managed by the
CPU.
The CPU can then access to the various Pipe registers and data.
24.6
Pipe configuration
The following flow (see Figure 24-3 on page 287) must be respected in order to activate a Pipe.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SJ80C32XXX-12SV | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| S80C52EXXX-20SHXXX:D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
| SCC9521002-01C | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| S80C52XXX-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| S80C32E-40SHXXX:RD | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC80C451ACN64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| SC80C451AGN64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| SC80C451CCA68 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O |
| SC80C451CCN64 | 制造商:NXP Semiconductors 功能描述: |
| SC80C451CGA68 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。