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參數(shù)資料
| 型號： | SC68C752B |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola mP interface |
| 中文描述： | 5伏，3.3伏和2.5伏兆5雙UART /秒（最大），64字節(jié)的FIFO和摩托羅拉手機接口 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大小： | 219K |
| 代理商： | SC68C752B |
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9397 750 14963
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2005
24 of 46
Philips Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.5 Line Status Register (LSR)
Table 14
shows the Line Status Register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically
exist, as the data read from the RX FIFO is output directly onto the output data bus,
D[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the
LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
Table 14:
Bit
7
Line Status Register bits description
Symbol
Description
LSR[7]
FIFO data error.
logic 0 = No error (normal default condition)
logic 1 = At least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold
and
shift registers are not empty
logic 1 = transmitter hold
and
shift registers are empty
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = Transmit Hold Register is
not
empty
logic 1 = Transmit Hold Register is empty. The processor can now load up to
64 bytes of data into the THR if the TX FIFO is enabled.
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = A break condition occurred and associated byte is 00, that is,
RX was LOW for one character time frame.
LSR[3]
Framing error.
logic 0 = no framing error in data being read from RX FIFO (normal default
condition)
logic 1 = Framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit.
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
LSR[0]
Data in receiver.
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
6
5
4
3
2
1
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC68C752BIB48 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48,128 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48,151 | 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48,157 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48-F | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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