參數(shù)資料
型號： SC68C752B
廠商： NXP Semiconductors N.V.
英文描述： 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola mP interface
中文描述： 5伏，3.3伏和2.5伏兆5雙UART /秒（最大），64字節(jié)的FIFO和摩托羅拉手機接口
文件頁數(shù)： 20/46頁
文件大?。?/td> 219K
代理商： SC68C752B
9397 750 14963
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2005
20 of 46
Philips Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 11
lists and describes the SC68C752B internal registers.
[1]
These registers are accessible only when LCR[7] = 0.
[2]
This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Table 11:
SC68C752B internal registers
A2 A1 A0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General register set
[1]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
bit 7
bit 7
0/CTS
interrupt
enable
[2]
RX
trigger
level
(MSB)
FCR[0]
bit 6
bit 6
0/RTS
interrupt
enable
[2]
RX
trigger
level
(LSB)
FCR[0]
bit 5
bit 5
0/Xoff
[2]
bit 4
bit 4
0/X Sleep
mode
[2]
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
bit 2
bit 2
receive
linestatus
interrupt
TX FIFO
reset
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
R
W
R/W
0
1
0
FCR
0/TX
trigger
level
(MSB)
[2]
0/CTS,
RTS
0/TX
trigger
level
(LSB)
[2]
0/Xoff
W
0
1
0
IIR
interrupt
priority
bit 2
parity
enable
interrupt
priority
bit 1
numberof
stop bits
interrupt
priority
bit 0
word
length
bit 1
RTS
interrupt
status
R
0
1
1
LCR
DLAB
break
control
bit
TCR and
TLR
enable
[2]
THR and
TSR
empty
RI
bit 6
bit 6
bit 6
0
set parity
parity
type
select
0/enable
loop-back
word
length
bit 0
DTR
R/W
1
0
0
MCR
1
×
or
1
×
/4
clock
[2]
0/error in
RX FIFO
0/Xon
Any
[2]
OPA/
OPB
control
framing
error
FIFO
ready
enable
parity
error
R/W
1
0
1
LSR
THR
empty
break
interrupt
overrun
error
data in
receiver
R
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
MSR
SPR
TCR
TLR
FIFO Rdy 0
CD
bit 7
bit 7
bit 7
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
CD
bit 3
bit 3
bit 3
0
RI
bit 2
bit 2
bit 2
0
DSR
bit 1
bit 1
bit 1
TX FIFO
B status
CTS
bit 0
bit 0
bit 0
TX FIFO
A status
R
R/W
R/W
R/W
R
Special register set
[3]
0
0
0
0
0
1
Enhanced register set
[4]
0
1
0
DLL
DLH
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
R/W
R/W
EFR
Auto
CTS
Auto
RTS
Special
character
detect
Enable
enhanced
functions
[2]
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
R/W
1
1
1
1
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
bit 5
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
bit 4
R/W
R/W
R/W
R/W
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SC68C752BIB48 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48,128 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48,151 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48,157 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48-F 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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