參數(shù)資料
型號(hào): SC28L92A1BS,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 48/73頁(yè)
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 44PQFP
標(biāo)準(zhǔn)包裝: 490
系列: IMPACT
特點(diǎn): 故障啟動(dòng)位檢測(cè)
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-HVQFN EP(6x6)
包裝: 托盤(pán)
其它名稱(chēng): 935281063551
SC28L92A1BS-S
SC28L92A1BS-S-ND
52
2552K–AVR–04/11
ATmega329/3290/649/6490
0x0004
jmp
PCINT0
; PCINT0 Handler
...
;
0x002C
jmp
SPM_RDY
; Store Program Memory Ready Handler
;
.org 0x3800/0x7800
0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start
0x3801/0x7801
out
SPH,r16
; Set Stack Pointer to top of RAM
0x3802/0x7802
ldi
r16,low(RAMEND)
0x3803/0x7803
out
SPL,r16
0x3804/0x7804
sei
; Enable interrupts
0x3805/0x7805
<instr>
xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address
Labels Code
Comments
;
.org 0x3800/0x7800
0x3800/0x7800
jmp
RESET
; Reset handler
0x3802/0x7802
jmp
EXT_INT0
; IRQ0 Handler
0x3804/0x7804
jmp
PCINT0
; PCINT0 Handler
...
;
0x382C/0x782C
jmp
SPM_RDY
; Store Program Memory Ready Handler
;
0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start
0x382F/0x782F
out
SPH,r16
; Set Stack Pointer to top of RAM
0x3830/0x7830
ldi
r16,low(RAMEND)
0x3831/0x7831
out
SPL,r16
0x3832/0x7832
sei
; Enable interrupts
0x3833/0x7833
<instr>
xxx
11.1.1
Moving Interrupts Between Application and Boot Space
The MCU Control Register controls the placement of the Interrupt Vector table.
11.2
Register Description
11.2.1
MCUCR – MCU Control Register
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write
Bit
7
654
32
10
JTD
PUD
IVSEL
IVCE
MCUCR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
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