參數(shù)資料
型號: SC28L92A1BS,551
廠商: NXP Semiconductors
文件頁數(shù): 39/73頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 44PQFP
標準包裝: 490
系列: IMPACT
特點: 故障啟動位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應商設備封裝: 48-HVQFN EP(6x6)
包裝: 托盤
其它名稱: 935281063551
SC28L92A1BS-S
SC28L92A1BS-S-ND
44
2552K–AVR–04/11
ATmega329/3290/649/6490
Figure 10-5. Brown-out Reset During Operation
10.6
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT. Refer to
page 45 for details on operation of the Watchdog Timer.
Figure 10-6. Watchdog Reset During Operation
10.7
Internal Voltage Reference
ATmega329/3290/649/6490 features an internal bandgap reference. This reference is used for
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
10.7.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in “System and Reset Characteristics” on page 330. To save power, the
reference is not always turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODLEVEL [1..0] Fuse).
2.
When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
VCC
RESET
TIME-OUT
INTERNAL
RESET
VBOT-
VBOT+
tTOUT
CK
CC
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