參數(shù)資料
型號(hào): SC28L198C1A
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cable Ties; Color:Black; Pack Quantity:100
中文描述: 8 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC84
封裝: PLASTIC, MO-047AF, SOT-189-3, LCC-84
文件頁(yè)數(shù): 21/56頁(yè)
文件大?。?/td> 345K
代理商: SC28L198C1A
Philips Semiconductors
Product specification
SC28L198
Octal UART for 3.3V and 5V supply voltage
1999 Jan 14
21
asserted (low), the character is transmitted. If it is negated (high),
the TxD output remains in the marking state and the transmission is
delayed until CTSN goes low. Changes in CTSN, while a character
is being transmitted, do not affect the transmission of that character.
This feature can be used to prevent overrun of a remote receiver.
MR2[3:2] –
RxINT control field
Controls when interrupt arbitration for a receiver begins based on
RxFIFO fill level. This field allows interrupt arbitration to begin when
the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1
character.
MR2[1:0] –
Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can
be programmed for character lengths of 6, 7, and 8 bits. For a
character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.
In all cases, the receiver only checks for a mark condition at the
center of the first stop bit position (one bit time after the last data bit,
or after the parity bit if parity is enabled). If an external 1X clock is
used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1]
= 1 selects two stop bits to be transmitted.
Table 6. RxCSR and TxCSR – Receiver and Transmitter Clock Select Registers
Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b’111. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown
below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.
Bits 7:5
Bits 4:0
Reserved
Transmitter/Receiver Clock select code, (see Clock Mux Table below)
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Table 7. Data Clock Mux
CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
Clock selection,
BRG – 75
00010
BRG – 150
00011
BRG – 200
BRG – 600
00111
BRG – 900
01000
BRG – 1200
01001
BRG – 1800
BRG – 3600
BRG – 4800
01101
BRG – 7200
01110
BRG – 9600
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Clock Select Code
11101
Clock Select Code
Reserved
BRG – 38.4K
BRG – 57.6K
G
1
BRG C/T 0
BRG C/T 1
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10001
10010
10011
10111
11000
11001
11011
11110
Reserved
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相關(guān)PDF資料
PDF描述
SC28C198A1A Octal UART for 3.3V and 5V supply voltage
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SC28L202 Dual universal asynchronous receiver/transmitter DUART
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