參數(shù)資料
型號(hào)： SC26L198
廠商： NXP Semiconductors N.V.
英文描述： Octal UART with TTL compatibility at 3.3V and 5V supply voltages
中文描述： 八路與TTL兼容的UART在3.3V和5V電源電壓
文件頁(yè)數(shù)： 26/49頁(yè)
文件大小： 358K
代理商： SC26L198
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
361
Table 33. Global Interrupting Type Register
Bit 7:6
10 – with receive errors
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Bit 5
Transmitter Interrupt
1 – transmitter interrupt
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Bit 4:3
Reserved
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Bit 2:0
001 – Change of State
011 – Xon/Xoff status
101 – Break Change
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CIR. It contains the type of interrupt code for all interrupts.
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Undefined when the CIR interrupt context is not a receiver interrupt.
Global TxFIFO Register
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The TxFIFO of the channel indicated in the CIR channel field.
Undefined when the CIR interrupt context is not a transmitter
interrupt. Writing to the GTxFIFO when the current interrupt is not a
transmitter event may result in the characters being transmitted on a
different channel than intended.
Bit 7
I/O3
1 – change
This register may be read to determine the current level of the I/O
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Bit 6
I/O2
1 – change
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Bit 7
I/O1
1 – change
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Bit 6
I/O0
1 – change
each pin. If the change detection is not enabled or if the pin is
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Bit 3
I/O3
1 = high level; 0 =– low level.
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Bit 2
I/O2
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Bit 1
I/O1
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Bit 0
I/O0
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Table 37. I/OPIOR – I/O Port Interrupt and Output Register
Bit 7
Bit 6
1 – enable
1 – enable
I/OPIOR[7:4] bits activate the input change of state detectors. If a
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Bit 5
1 – enable
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Bit 4
1 – enable
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Bit 3
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Bit 2
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Bit 1
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Bit 0
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I/OPIOR[3:0] bits hold the datum which is the inverse of the datum
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00 – GPI/TxC input
01 – I/OPIOR[3] output
11 – TxC1x output
* If I/OPCR(5:4) is programmed as ’01’ then the RTSN functionality
is assigned to I/O2, otherwise, this function can be implemented on
I/O1. (This allows for a lower pin count package option)
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00 – GPI/RxC input
01 – I/OPIOR[2]/RTSN *
11 – RxC16x output
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00 – GPI input
01 – I/OPIOR[1]/RTSN *
11 – RxC1x output
power up or reset. Inputs may be used as RxC, TxC inputs or
CTSN and General Purpose Inputs simultaneously. All inputs are
equipped with change detectors that may be used to generate
interrupts or can be polled, as required.
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00 – GPI/CTSN input
01 – I/OPIOR[0]output
11 – TxC16x output
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This register contains 4, 2 bit fields that set the direction and source
for each of the I/O pins associated with the channel. The I/O2
output may be RTSN if MR1[7] is set, or may signal ”end of
transmission” if MR2[5] is set.(Please see the descriptions of these
functions under the MR1 and MR2 register descriptions) If this
control bit is cleared, the pin will use the OPR[2] as a source if
I/OPCR[5:4] is b’01. The b’00 combinations are always inputs. This
register resets to x’0, effectively configuring all I/O pins as inputs on
NOTE: To ensure that CTSN, RTSN and an external RxC are
always available, if I/O2 is not selected as the RTSN output, the
RTSN function is automatically provided on I/O1.
GENERAL PURPOSE OUTPUT PIN CONTROL
The following four registers control the function of the G
OUT
0 pin.
These output pins have a unique control matrix which includes a
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