參數(shù)資料
型號： SC26L198
廠商： NXP Semiconductors N.V.
英文描述： Octal UART with TTL compatibility at 3.3V and 5V supply voltages
中文描述： 八路與TTL兼容的UART在3.3V和5V電源電壓
文件頁數(shù)： 20/49頁
文件大?。?/td> 358K
代理商： SC26L198
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
355
01101
Block error status mode. Upon reset of the device or an
individual receiver, the block mode of receiver error status
accumulates as each character moves to the bottom of
the RxFIFO, the position from which it will be read. In this
mode of operation, the RxFIFO may contain a character
with non–zero error status for some time. The status will
not reflect the error character’s presence until it is ready to
be popped from the RxFIFO. Command 01101 allows the
error status to be updated as each character is
pushed
into the RxFIFO. This allows the earliest detection of a
problem character, but complicates the determination of
exactly which character is causing the error. This mode of
block error accumulation may be exited only by resetting
the chip or the individual receiver.
Reserved.
Transmit an Xon Character
Transmit an Xoff Character
Reserved for channels b–h, for channel a: enables a
Gang Write of Xon Character Registers. After this
command is issued, a write to the channel A Xon
Character Register will result in a write to
all
channel’s
Xon character registers. This command provides a
mechanism to initialize all the Xon Character registers
with one write. A write to channel A Xon Character
Register returns the Octal UART to the individual Xon
write mode.
Reserved for channels b–h, for channel a: enables Gang
Write of Xoff Character Registers. After this command is
issued, a write to the channel A Xoff Character Register
will result in a write to
all
channel’s Xoff character
registers. This command provides a mechanism to
initialize all the Xoff Character registers with one write. A
write to channel A Xoff Character Register returns the
Octal UART to the individual Xoff write mode.
Note: Gang writing of Xon/Xoff Character Commands: Issuing
command causes the next write to Xon/Xoff Character Register
A to effect a simultaneous write into the other 3 Xon/Xoff
character registers. After the Xon/Xoff Character Register A is
written, the 26C198 returns to individual write mode for the
Xon/Xoff Character Registers. Other intervening reads and
writes are ignored. The device resets to individual write mode.
10100 Reserved for channels b-h, for channel a: executes a Gang
Load of Xon Character Registers. Executing this
command causes a write of the value x’11 to
all
channel’s
Xon character registers. This command provides a
01111
10000
10001
10010
10011
mechanism to initialize all the Xon Character registers to a
default value with one write. Execution of this command
is immediate and does not effect the timing of subsequent
host I/O operations.
Reserved for channels b-h, for channel a: executes a
Gang Load of Xoff Character Registers. Executing this
command causes a write of the value x’13 to
all
channel’s
Xoff character registers. This command provides a
mechanism to initialize all the Xoff Character registers to a
default value with one write. Execution of this command
is immediate and does not effect the timing of subsequent
host I/O operations.
Xoff resume command (CRXoffre; not active in
“Auto-Transmit Mode”). A command to cancel a previous
Host Xoff command. Upon receipt, the channel’s
transmitter will transfer a character, if any, from the
TxFIFO and begin transmission.
Host Xoff command (CRXoff). This command allows tight
host CPU control of the flow control of the channel
transmitter. When interrupted for receipt of an Xoff
character by the receiver, the host may stop transmission
of further characters by the channel transmitter by issuing
the Host Xoff command. Any character that has been
transferred to the TxD shift register will complete its
transmission, including the stop bit.
Cancel Host transmit flow control command. Issuing this
command will cancel a previous transmit command if the
flow control character is not yet loaded into the TxD Shift
Register. If there is no character waiting for transmission
or if its transmission has already begun, then this
command has no effect.
11001–11011
Reserved
11011 Reset Address Recognition Status. This command clears the
interrupt status that was set when an address character
was recognized by a disabled receiver operating in the
special mode.
11100–11101
Reserved
11110
Resets all UART channel registers. This command
provides a means to zero all the UART channels that are
not reset to x’00 by a reset command or a hardware reset.
11111
Reserved for channels b-h, for channel a: executes a chip
wide reset. Executing this command in channel a is
equivalent to a hardware reset with the RESETN pin.
Executing in channel b-h, has no effect.
10101
10110
10111
11000
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