參數(shù)資料
型號(hào): SC2441EVB
廠商: Semtech Corporation
英文描述: Very Low Input Voltage 2-Phase Synchronous Step-down Controllers with Step-up Converter
中文描述: 非常低的輸入電壓2相同步降壓與升壓轉(zhuǎn)換器控制器
文件頁(yè)數(shù): 17/35頁(yè)
文件大?。?/td> 733K
代理商: SC2441EVB
17
2005 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
Applications Information (Cont.)
SC2441
.
I
2
1
R
v
o
esr
ESR
δ
+
=
The peak-to-peak input voltage ripple due to the capacitor
is
.
f
C
DI
v
s
in
o
C
From these two expressions, C
can be found to meet the
input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce ripple.
The two step-down channels of the SC2441 operate at
180 degrees from each other. If both step-down channels
in the SC2441 are connected in parallel, both the input
and the output RMS currents will be reduced.
Ripple cancellation effect of interleaving allows the use of
smaller input capacitors. When converter outputs are
connected in parallel and interleaved, smaller inductors
and capacitors can be used for each channel. The total
output ripple-voltage remains unchanged. Smaller
inductors speeds up output load transient.
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the individual
DC input currents. The combined input current waveform
depends on duty ratio and the output current waveform.
Assuming that the output current ripple is small, the
following formula can be used to estimate the
RMS
value
of the ripple current in the input capacitor.
Let the duty ratios and output currents of Channel 1 and
Channel 2 be D
1
, D
2
and I
o1
, I
o2
respectively.
If D
1
<0.5 and D
2
<0.5, then
.
I
D
I
D
I
2
2
o
2
2
1
o
1
Cin
+
If D
1
>0.5 and (D
1
-0.5) < D
2
<0.5, then
.
I
5
D
D
(
)
I
I
)(
5
D
(
I
I
2
2
o
1
2
2
2
o
1
o
1
2
1
o
Cin
+
+
+
+
If D
1
>0.5 and D
2
< (D
1
-0.5) < 0.5, then
.
I
5
D
D
(
)
I
I
2
D
I
I
2
2
o
2
1
2
2
o
1
o
2
1
o
Cin
+
+
+
If D
1
>0.5 and D
2
> 0.5, then
.
I
1
D
1
I
2
D
1
)
I
I
)(
1
D
D
(
I
2
2
o
2
1
o
2
2
o
1
o
2
1
Cin
+
+
+
+
Power MOSFET Selection and Gate Drive
Main considerations in selecting the MOSFET’s are power
dissipation, cost and packaging. Switching losses and
conduction losses of the MOSFET’s are directly related to
the total gate charge (
C
) and channel on-resistance
(
R
). In order to judge the performance of MOSFET’s,
the product of the total gate charge and on-resistance is
used as a figure of merit (FOM). Transistors with the same
FOM follow the same curve in Figure 10.
0
1
5
10
Rds
15
20
20
0
20
40
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
On-resistance (mOhm)
G
50
1
Cg 100 Rds
(
)
Cg 200 Rds
(
)
Cg 500 Rds
(
)
Figure 10. Figure of merit curves.
The closer the curve is to the origin, the lower is the FOM.
This means lower switching loss or lower conduction loss
or both. It may be difficult to find MOSFET’s with both low
C
and low
R
. Usually a trade-off between
R
ds(on
and
C
g
has to be made.
MOSFET selection also depends on applications. In many
applications, either switching loss or conduction loss
dominates for a particular MOSFET. For synchronous buck
converters with high input to output voltage ratios, the top
MOSFET is hard switched but conducts with very low duty
cycle. The bottom switch conducts at high duty cycle but
switches at near zero voltage. For such applications,
MOSFET’s with low
C
g
are used for the top switch and
MOSFET’s with low R
ds(on)
are used for the bottom switch.
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