參數(shù)資料
型號: SC16IS760IBS
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù): 41/62頁
文件大?。?/td> 308K
代理商: SC16IS760IBS
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
41 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
10.3 Addressing
Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The first byte after the START condition carries the address of
the slave device and the read/write bit.
Table 32
shows how the SC16IS740/750/760’s
address can be selected by using A1 and A0 pins. For example, if these 2 pins are
connected to V
DD
, then the SC16IS740/750/760’s address is set to 0x90, and the master
communicates with it through this address.
[1]
X = logic 0 for write cycle; X = logic 1 for read cycle.
10.4 Use of subaddresses
When a master communicates with the SC16IS740/750/760 it must send a subaddress in
the byte following the slave address byte. This subaddress is the internal address of the
word the master wants to access for a single byte transfer, or the beginning of a sequence
of locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device
address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus
it must be followed by an acknowledge.
Table 33
shows the breakdown of the subaddress (register address) byte. Bit 0 is not
used, bits [2:1] are both set to zeroes, bits [6:3] are used to select one of the device’s
internal registers, and bit 7 is not used.
A register write cycle is shown in
Figure 22
. The START is followed by a slave address
byte with the direction bit set to ‘write’, a subaddress byte, a number of data bytes, and a
STOP signal. The subaddress indicates which register the master wants to access, and
the data bytes which follow will be written one after the other to the subaddress location.
Table 32.
A1
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SC16IS740/750/760 address map
A0
SC16IS750/760 I
2
C addresses (hex)
[1]
V
DD
0x90 (1001 000X)
V
SS
0x92 (1001 001X)
SCL
0x94 (1001 010X)
SDA
0x96 (1001 011X)
V
DD
0x98 (1001 100X)
V
SS
0x9A (1001 101X)
SCL
0x9C (1001 110X)
SDA
0x9E (1001 111X)
V
DD
0xA0 (1010 000X)
V
SS
0xA2 (1010 001X)
SCL
0xA4 (1010 010X)
SDA
0xA6 (1010 011X)
V
DD
0xA8 (1010 100X)
V
SS
0xAA (1010 101X)
SCL
0xAC (1010 110X)
SDA
0xAE (1010 111X)
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