參數(shù)資料
型號(hào): SC16IS752IPW
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 40/60頁
文件大小: 356K
代理商: SC16IS752IPW
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 1 September 2011
40 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
The register read cycle (see
Figure 19
) commences in a similar manner, with the master
sending a slave address with the direction bit set to WRITE with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a Repeated
START followed again by the device address, but this time with the direction bit set to
READ. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is
terminated by a STOP signal.
Table 33.
Bit
7
6:3
2:1
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
(1) See
Table 33
for additional information.
Fig 18. Master writes to slave
S
SLAVE ADDRESS
002aab047
W
A
REGISTER ADDRESS
(1)
A
nDATA
A
P
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
(1) See
Table 33
for additional information.
Fig 19. Master read from slave
S
SLAVE ADDRESS
002aab048
W
A
REGISTER ADDRESS
(1)
A
NA
P
S
SLAVE ADDRESS
R
A
nDATA
A
LAST DATA
Register address byte (I
2
C)
Name
-
A[3:0]
CH1, CH0
Function
not used
UART’s internal register select
Channel select.
00 = channel A
01 = channel B
10 = reserved
11 = reserved
not used
0
-
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