參數(shù)資料
型號(hào)： SC16IS752IPW
廠商： NXP Semiconductors N.V.
元件分類： 連接器件
英文描述： Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝： SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù)： 23/60頁(yè)
文件大?。?/td> 356K
代理商： SC16IS752IPW
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 1 September 2011
23 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1]
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
8.4 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels.
Table 12
shows FIFO Control Register bit settings.
Table 12.
Bit
7:6
[1]
FIFO reset logic requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of
the XTAL1 clock.
1
IER[1]
Transmit Holding Register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
Receive Holding Register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
0
IER[0]
Table 11.
Bit
Interrupt Enable Register bits description
…continued
Symbol
Description
FIFO Control Register bits description
Symbol
Description
FCR[7] (MSB),
FCR[6] (LSB)
00 = 8 characters
01 = 16 characters
10 = 56 characters
11 = 60 characters
FCR[5] (MSB),
FCR[4] (LSB)
00 = 8 spaces
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
FCR[3]
reserved
FCR[2]
[1]
Reset TX FIFO.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
level logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
FCR[1]
[1]
Reset RX FIFO
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
level logic (the Receive Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
FCR[0]
FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO
RX trigger. Sets the trigger level for the RX FIFO.
5:4
TX trigger. Sets the trigger level for the TX FIFO.
3
2
1
0
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參數(shù)描述
SC16IS752IPW,112 功能描述:UART 接口集成電路 UART DUAL 12C/SPI RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS752IPW,128 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS752IPW112 制造商:NXP Semiconductors 功能描述:IC DUAL UART FIFO 5MBPS 3.6V TSSOP28
SC16IS752IPW128 制造商:NXP Semiconductors 功能描述:
SC16IS752IPW-F 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE W/IRDA AND GPIO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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