參數(shù)資料
型號: SC16C850VIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
封裝: SC16C850VIBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16C850VIBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
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代理商: SC16C850VIBS
SC16C850V
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 19 January 2011
27 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.8 Modem Status Register (MSR)
This register shares the same address as EFCR register. This is a read-only register and
it provides the current state of the control interface signals from the modem, or other
peripheral device to which the SC16C850V is connected. Four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
When write, the data will be written to EFCR register.
Table 21.
Bit
7
[1]
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
0
LSR[0]
Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic 1 = data has been received and is saved in the Receive Holding Register
or FIFO
Table 20.
Bit
Line Status Register bits description
…continued
Symbol
Description
Modem Status Register bits description
Symbol
Description
MSR[7]
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the loopback mode produces the state of MCR[3] (OP2).
MSR[6]
RI. During normal operation, this bit is the complement of the RI input. Reading
this bit in the loopback mode produces the state of MCR[2] (OP1).
MSR[5]
DSR. During normal operation, this bit is the complement of the DSR input.
During the loopback mode, this bit is equivalent to MCR[0] (DTR).
MSR[4]
CTS. During normal operation, this bit is the complement of the CTS input.
During the loopback mode, this bit is equivalent to MCR[1] (RTS).
MSR[3]
Δ
CD
[1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C850V has changed state since the last
time it was read. A modem Status Interrupt will be generated.
MSR[2]
Δ
RI
[1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C850V has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
MSR[1]
Δ
DSR
[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C850V has changed state since the last
time it was read. A modem Status Interrupt will be generated.
MSR[0]
Δ
CTS
[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C850V has changed state since the last
time it was read. A modem Status Interrupt will be generated.
6
5
4
3
2
1
0
相關(guān)PDF資料
PDF描述
SC16C852LIB 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIBS 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIET 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852SVIET 1.8 V dual UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
SC16C852VIET 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and XScale VLIO bus interface
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