參數(shù)資料
型號: SC16C850SVIBS
廠商: NXP SEMICONDUCTORS
元件分類: DRAM
英文描述: 1.8 V single UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
中文描述: 128 X 8 BI-DIRECTIONAL FIFO, PDSO32
封裝: 5 X 5 MM, 0.85 MM PITCH, ROHS COMPLIANT, MO-220, HVQFN-32
文件頁數(shù): 22/48頁
文件大小: 911K
代理商: SC16C850SVIBS
SC16C850SV
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 22 March 2011
22 of 48
NXP Semiconductors
SC16C850SV
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger
levels.
7.3.1
FIFO mode
Table 9.
Bit
7:6
[1]
For 128-byte FIFO mode, refer to
Section 7.16
,
Section 7.17
,
Section 7.18
.
[2]
For 128-byte FIFO mode, refer to
Section 7.15
,
Section 7.17
,
Section 7.18
.
Table 10.
FCR[7]
0
0
1
1
[1]
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see
Section 6.4 “FIFO operation”
.
FIFO Control Register bits description
Symbol
Description
FCR[7:6]
Receive trigger level in 32-byte FIFO mode.
[1]
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C850SV will issue a receive ready interrupt when the number
of characters in the receive FIFO reaches the selected trigger level. Refer to
Table 10
.
FCR[5:4]
Transmit trigger level in 32-byte FIFO mode.
[2]
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850SV will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 11
.
FCR[3]
reserved
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
5:4
3
2
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
0
FCR[0]
RCVR trigger levels
FCR[6]
0
1
0
1
RX FIFO trigger level in 32-byte FIFO mode
[1]
8 bytes
16 bytes
24 bytes
28 bytes
相關(guān)PDF資料
PDF描述
SC16C850VIBS 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
SC16C852LIB 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIBS 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIET 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852SVIET 1.8 V dual UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
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SC16C850SVIBS,118 功能描述:UART 接口集成電路 UART 1-CH 128Byte FIFO 1.8V 32-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850SVIBS,151 功能描述:UART 接口集成電路 UART 1-CH 128Byte FIFO 1.8V 32-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850SVIBS,157 功能描述:UART 接口集成電路 UART 1-CH 128Byte FIFO 1.8V 32-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850V 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface