參數(shù)資料
型號: SC16C850IET
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
封裝: SC16C850IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16C850IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<
文件頁數(shù): 40/55頁
文件大小: 394K
代理商: SC16C850IET
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
40 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
Maximum frequency =
[3]
1 k
Ω
pull-up resistor on IRQ pin.
[4]
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Table 38.
T
amb
=
40
°
C to +85
°
C; tolerance of V
DD
±
10 %; unless otherwise specified.
Symbol
Parameter
Dynamic characteristics - Motorola or 68 mode
Conditions
V
DD
= 2.5 V
Min
6
6
12.5
-
10
15
10
10
50
20
-
-
V
DD
= 3.3 V
Min
6
6
12.5
-
10
15
10
10
20
10
-
-
Unit
Max
-
-
-
80
-
-
-
-
-
-
50
20
Max
-
-
-
80
-
-
-
-
-
-
20
20
t
WH
t
WL
t
w(clk)
f
XTAL1
t
su(A)
t
h(A)
t
su(RWL-CSL)
t
su(RWH-CSL)
t
w(CS)
t
d(CS)
t
d(CS-Q)
t
dis(CS-QZ)
pulse width HIGH
pulse width LOW
clock pulse width
frequency on pin XTAL1
address set-up time
address hold time
set-up time from R/W LOW to CS LOW
set-up time from R/W HIGH to CS LOW
CS pulse width
CS delay time
delay time from CS to data output
disable time from CS to
high-impedance data output
hold time from CS to R/W HIGH
R/W delay time
set-up time from data input to CS HIGH
data input hold time after CS HIGH
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
[1][2]
25 pF load
25 pF load
25 pF load
25 pF load
t
h(CS-RWH)
t
d(RW)
t
su(D-CSH)
t
h(CSH-D)
t
d(modem-IRQL)
t
d(CS-IRQH)R
t
d(stop-IRQL)
t
d(CS-TX)W
t
d(start-IRQL)
t
d(CS-IRQH)W
t
d(CS-Q)W
t
w(RESET_N)
N
10
10
15
15
-
-
-
-
10
10
15
15
-
-
-
-
ns
ns
ns
ns
delay time from modem to IRQ LOW
read delay time from CS to IRQ HIGH
delay time from stop to IRQ LOW
write delay time from CS to TX
delay time from start to IRQ LOW
write delay time from CS to IRQ HIGH
write delay time from CS to data output
pulse width on pin RESET
baud rate divisor
[3]
-
-
-
40
40
-
-
-
30
30
ns
ns
s
[3]
[4]
1T
RCLK
24T
RCLK
1T
RCLK
55
40
-
(2
16
1)
1T
RCLK
24T
RCLK
s
1T
RCLK
45
33
-
(2
16
1)
[4]
8T
RCLK
-
-
-
10
1
8T
RCLK
-
-
-
10
1
[3][4]
s
ns
ns
ns
[3]
t
w clk
)
--------------
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