參數(shù)資料
型號: SC16C752IB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: Dual UART with 64-byte FIFO
封裝: SC16C752IB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<week 17, 2005,;
文件頁數(shù): 21/47頁
文件大?。?/td> 604K
代理商: SC16C752IB48
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
21 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.3 FIFO control register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs,
setting transmitter and receiver trigger levels, and selecting the type of DMA
signalling.
Table 11
shows FIFO control register bit settings.
Table 11:
Bit
7-6
FIFO Control Register bits description
Symbol
Description
FCR[7]
(MSB),
FCR[6]
(LSB)
10 - 56 characters
11 - 60 characters
FCR[5]
(MSB),
FCR[4]
(LSB)
10 - 32 spaces
11 - 56 spaces
FCR[5-4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’
Logic 1 = Set DMA mode ‘1’
FCR[2]
Reset TX FIFO.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
FCR[1]
Reset RX FIFO.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
FCR[0]
FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
RCVR trigger. Sets the trigger level for the RX FIFO.
00 - 8 characters
01 - 16 characters
5-4
TX trigger. Sets the trigger level for the TX FIFO.
00 - 8 spaces
01 - 16 spaces
3
2
1
0
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