參數(shù)資料
型號(hào): SC16C750IB64
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 13/45頁(yè)
文件大?。?/td> 598K
代理商: SC16C750IB64
Philips Semiconductors
SC16C750
UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
13 of 45
9397 750 11623
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.6 DMA operation
The SC16C750 FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables
6
and
7
show this.
Table 5:
Using 1.8432 MHz crystal
Desired
baud rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
Baud rates using 1.8432 MHz or 3.072 MHz crystal
Using 3.072 MHz crystal
Desired
baud rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
Divisor for
16
×
clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
Baud rate
error
Divisor for
16
×
clock
3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5
Baud rate
error
0.026
0.058
0.026
0.034
0.312
0.69
0.628
1.23
2.86
Table 6:
Non-DMA mode
1 = FIFO empty
0 = at least 1 byte in FIFO
Effect of DMA mode on state of RXRDY pin
DMA mode
0-to-1 transition when FIFO empties
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 7:
Non-DMA mode
1 = at least 1 byte in FIFO
0 = FIFO empty
Effect of DMA mode on state of TXRDY pin
DMA mode
0-to-1 transition when FIFO becomes full
1-to-0 transition when FIFO goes below trigger level
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SC16C751B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
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