參數(shù)資料
型號(hào): SC16C750IA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁(yè)數(shù): 16/45頁(yè)
文件大小: 598K
代理商: SC16C750IA44
Philips Semiconductors
SC16C750
UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
16 of 45
9397 750 11623
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Table 8
details the assigned bit functions for the fifteen SC16C750 internal registers.
The assigned bit functions are more fully defined in
Section 7.1
through
Section 7.11
.
[1]
[2]
[3]
[4]
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register is accessible only when LCR is set to ‘BF
Hex
’.
Table 8:
A2
General Register Set
[2]
0
0
0
0
0
0
0
0
1
SC16C750 internal registers
A0
Register Default
[1]
Bit 7
A1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RHR
THR
IER
XX
XX
00
bit 7
bit 7
0
bit 6
bit 6
0
bit 5
bit 5
low
power
mode
bit 4
bit 4
Sleep
mode
bit 3
bit 3
modem
status
interrupt
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
bit 1
bit 1
transmit
holding
register
bit 0
bit 0
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
64-byte
FIFO
enable
64-byte
FIFO
enable
reserved
DMA
mode
select
INT
priority
bit 2
parity
enable
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
FIFO
enable
0
1
0
ISR
01
0
INT
status
0
1
1
LCR
00
divisor
latch
enable
0
set break set parity even
parity
word
length
bit 0
DTR
1
0
0
MCR
00
0
reserved loop back OUT2,
INT
enable
framing
error
OUT1
1
0
1
LSR
60
FIFO
data
error
DCD
bit 7
trans.
empty
trans.
holding
empty
DSR
bit 5
break
interrupt
parity
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special Register Set
[3]
0
0
0
0
0
1
Enhanced Register Set
[4]
0
1
0
1
1
0
1
MSR
SPR
X0
FF
RI
bit 6
CTS
bit 4
DCD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
XX
XX
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
EFR
00
Auto
CTS
Auto RTS 0
0
0
0
0
0
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