參數(shù)資料
型號: SC16C750IA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 11/45頁
文件大小: 598K
代理商: SC16C750IA44
Philips Semiconductors
SC16C750
UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
11 of 45
9397 750 11623
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.3 Hardware flow control
When automatic hardware flow control is enabled, the SC16C750 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, the SC16C750 will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out. Transmission is resumed after the
CTS input returns to a logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger level. However, under the above described conditions,
the SC16C750 will continue to accept data until the receive FIFO is full.
6.4 Time-out interrupts
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C750 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
64-byte FIFO
1
16
32
56
1
16
32
56
16
32
56
60
1
8
16
32
Table 4:
Selected trigger level
(characters)
Flow control mechanism
…continued
INT pin activation
Negate RTS
Assert RTS
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