參數(shù)資料
型號: SC16C654B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大),64字節(jié)的FIFO和紅外線(IrDA)編碼器/解碼器
文件頁數(shù): 34/58頁
文件大小: 302K
代理商: SC16C654B
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
34 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C654B/654DB is connected. Four bits of this
register are used to indicate the changed information. These bits are set to a logic 1
whenever a control input from the modem changes state. These bits are set to a logic 0
whenever the CPU reads this register.
[1]
Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.
Table 21:
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
CD (active HIGH, logical 1). Normally this bit is the complement of the CD
input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR
register.
MSR[6]
RI (active HIGH, logical 1). Normally this bit is the complement of the RI input.
In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register.
MSR[5]
DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR
input. In loop-back mode this bit is equivalent to the DTR bit in the MCR
register.
MSR[4]
CTS. CTS functions as hardware flow control signal input if it is enabled via
EFR[7]. The transmit holding register flow control is enabled/disabled by
MSR[4]. Flow control (when enabled) allows starting and stopping the
transmissions based on the external modem CTS signal. A logic 1 at the CTS
pin will stop SC16C654B/654DB transmissions as soon as current character
has finished transmission. Normally MSR[4] is the complement of the CTS
input. However, in the loop-back mode, this bit is equivalent to the RTS bit in
the MCR register.
MSR[3]
CD
[1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C654B/654DB has changed state since
the last time it was read. A modem Status Interrupt will be generated.
MSR[2]
RI
[1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C654B/654DB has changed from a logic 0
to a logic 1. A modem Status Interrupt will be generated.
MSR[1]
DSR
[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C654B/654DB has changed state since
the last time it was read. A Modem Status Interrupt will be generated.
MSR[0]
CTS
[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C654B/654DB has changed state since
the last time it was read. A Modem Status Interrupt will be generated.
6
5
4
3
2
1
0
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