參數(shù)資料
型號： SC16C654B
廠商： NXP Semiconductors N.V.
英文描述： 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder
中文描述： 5伏，3.3伏和2.5伏兆5四異步/秒（最大），64字節(jié)的FIFO和紅外線（IrDA）編碼器/解碼器
文件頁數(shù)： 24/58頁
文件大?。?/td> 302K
代理商： SC16C654B
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
24 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.
Register descriptions
Table 8
details the assigned bit functions for the SC16C654B/654DB internal registers.
The assigned bit functions are more fully defined in
Section 7.1
through
Section 7.11
.
[1]
The value shown represents the register’s initialized HEX value; X = not applicable.
[2]
These registers are accessible only when LCR[7] = 0.
[3]
These bits are only accessible when EFR[4] is set.
[4]
This function is not supported in the HVQFN48 package; TXRDY and RXRDY are removed.
[5]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
[6]
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
Table 8:
A2 A1 A0 Register Default
[1]
Bit 7
General Register Set
[2]
0
0
0
RHR
0
0
0
THR
0
0
1
IER
SC16C654B/654DB internal registers
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XX
XX
00
bit 7
bit 7
CTS
interrupt
[3]
bit 6
bit 6
RTS
interrupt
[3]
bit 5
bit 5
Xoff
interrupt
[3]
bit 4
bit 4
Sleep
mode
[3]
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
[4]
INT
priority
bit 2
parity
enable
bit 2
bit 2
receive
line status
interrupt
XMIT
FIFO reset
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
bit 0
bit 0
receive
holding
register
FIFO
enable
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
TX
trigger
(MSB)
[3]
INT
priority
bit 4
set parity even
TXtrigger
(LSB)
[3]
0
1
0
ISR
01
INT
priority
bit 3
INT
priority
bit 1
stop bits
INT
status
0
1
1
LCR
00
divisor
latch
enable
Clock
select
[3]
FIFO
data
error
CD
bit 7
set
break
parity
word
length
bit 0
DTR
1
0
0
MCR
00
IR
enable
[3]
trans.
empty
Xon
Any
[3]
trans.
holding
empty
DSR
bit 5
loop back OP2, INTx
enable
framing
error
OP1
1
0
1
LSR
60
break
interrupt
parity
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special Register Set
[5]
0
0
0
0
0
1
Enhanced Register Set
[6]
0
1
0
1
1
0
1
MSR
SPR
X0
FF
RI
bit 6
CTS
bit 4
CD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
XX
XX
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
IER[4:7],
ISR[4:5],
FCR[4:5],
MCR[5:7]
bit 4
bit 12
bit 4
bit 12
Cont-3 Tx,
Rx Control
Cont-2Tx,
Rx Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
1
1
1
0
0
1
1
0
1
0
1
Xon-1
Xon-2
Xoff-1
Xoff-2
00
00
00
00
bit 7
bit 15
bit 7
bit 15
bit 6
bit 14
bit 6
bit 14
bit 5
bit 13
bit 5
bit 13
bit 3
bit 11
bit 3
bit 11
bit 2
bit 10
bit 2
bit 10
bit 1
bit 9
bit 1
bit 9
bit 0
bit 8
bit 0
bit 8
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