參數(shù)資料
型號(hào): SC16C652BIBS,151
廠商: NXP Semiconductors
文件頁數(shù): 21/21頁
文件大?。?/td> 0K
描述: IC ENCODER/DECODER IRDA 32HVQFN
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): 2 通道
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
其它名稱: 935276387151
SC16C652BIBS-S
SC16C652BIBS-S-ND
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
9 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.3 FIFO operation
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger level, but not
the transmit trigger level. The SC16C652B provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C2550, the transmit interrupt
trigger level is set to 16 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR, but activation will not take place until EFR[4]
is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
6.4 Hardware ow control
When automatic hardware ow control is enabled, the SC16C652B monitors the CTS pin
for a remote buffer overow indication and controls the RTS pin for local buffer overows.
Automatic hardware ow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C652B will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data may
be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC16C652B will continue to accept data until the receive FIFO is full.
6.5 Software ow control
When software ow control is enabled, the SC16C652B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC16C652B will halt transmission
(TX) as soon as the current character(s) has completed transmission. When a match
occurs, the receive ready (if enabled via Xoff IER[5]) ags will be set and the interrupt
output pin (if receive interrupt is enabled) will be activated. Following a suspension due to
a match of the Xoff characters’ values, the SC16C652B will monitor the receive data
stream for a match to the Xon1/Xon2 character value(s). If a match is found, the
SC16C652B will resume operation and clear the ags (ISR[4]).
Table 5:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
RX
TX
88
16
8
0
16
8
16
7
24
15
28
30
28
23
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