參數(shù)資料
型號: SC16C652BIBS,151
廠商: NXP Semiconductors
文件頁數(shù): 20/21頁
文件大?。?/td> 0K
描述: IC ENCODER/DECODER IRDA 32HVQFN
標準包裝: 490
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-HVQFN(5x5)
包裝: 托盤
其它名稱: 935276387151
SC16C652BIBS-S
SC16C652BIBS-S-ND
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
8 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.1 UART A-B functions
The UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC16C652B package, and an external serial device. A
logic 0 on chip select pins CSA and/or CSB allows the user to congure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are shown
6.2 Internal registers
The SC16C652B provides two sets of internal registers (A and B) consisting of
17 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4. The UART registers function as data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a
user accessible Scratchpad Register (SPR).
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
[3]
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when the LCR is set to ‘BFh’.
Table 3:
Serial port selection
Chip Select
Function
CSA-CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
Table 4:
Internal registers decoding
A2
A1
A0
Read mode
Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR) [1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM) [2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2) [3]
0
1
0
Enhanced Feature Register
1
0
Xon1 word
1
0
1
Xon2 word
1
0
Xoff1 word
1
Xoff2 word
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