參數(shù)資料
型號(hào)： SC16C554IB80
廠(chǎng)商： NXP Semiconductors N.V.
元件分類(lèi)： 收發(fā)器
英文描述： Quad UART with 16-byte FIFO and infrared (IrDA) encoder-decoder
封裝： SC16C554IB80<SOT315-1 (LQFP80)|<<http://www.nxp.com/packages/SOT315-1.html<1<week 17, 2005,;
文件頁(yè)數(shù)： 27/55頁(yè)
文件大?。?/td> 276K
代理商： SC16C554IB80
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
27 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C554/554D provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.
Table 12 “Interrupt source”
shows the data values
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12:
Priority
level
1
Interrupt source
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
0
0
0
1
1
0
LSR (Receiver Line Status
Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal) / Special character
CTS, RTS change of state
2
0
0
0
1
0
0
2
0
0
1
1
0
0
3
0
0
0
0
1
0
4
0
0
0
0
0
0
5
0
1
0
0
0
0
6
1
0
0
0
0
0
Table 13:
Bit
7:6
Interrupt Status Register bits description
Symbol
Description
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
ISR[5:4]
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
ISR[3:1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
Table 12
).
Logic 0 or cleared = default condition.
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
5:4
3:1
0
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