參數(shù)資料
型號(hào)： SC16C554IB80
廠商： NXP Semiconductors N.V.
元件分類： 收發(fā)器
英文描述： Quad UART with 16-byte FIFO and infrared (IrDA) encoder-decoder
封裝： SC16C554IB80<SOT315-1 (LQFP80)|<<http://www.nxp.com/packages/SOT315-1.html<1<week 17, 2005,;
文件頁(yè)數(shù)： 12/55頁(yè)
文件大?。?/td> 276K
代理商： SC16C554IB80
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
12 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
RXA, RXB,
RXC, RXD
7, 29,
41, 63
62, 20,
29, 51
17, 44,
57, 4
I
Receive data input RXA-RXD.
These inputs are associated with
individual serial channel data to the SC16C554/554D. The RX signal
will be a logic 1 during reset, idle (no data), or when the transmitter is
disabled. During the local loop-back mode, the RX input pin is
disabled and TX data is connected to the UART RX input internally.
Receive Ready (Active-LOW).
RXRDY contains the wire-ORed
status of all four receive channel FIFOs, RXRDYA-RXRDYD. A
logic 0 indicates receive data ready status, i.e., the RHR is full, or the
FIFO has one or more RX characters available for unloading. This
pin goes to a logic 1 when the FIFO/RHR is empty, or when there are
no more characters available in either the FIFO or RHR. Individual
channel RX status is read by examining individual internal registers
via CS and A0-A4 pin functions.
Transmit data A, B, C, D.
These outputs are associated with
individual serial transmit channel data from the SC16C554/554D.
The TX signal will be a logic 1 during reset, idle (no data), or when
the transmitter is disabled. During the local loop-back mode, the TX
output pin is disabled and TX data is internally connected to the
UART RX input.
Transmit Ready (Active-LOW).
TXRDY contains the wire-ORed
status of all four transmit channel FIFOs, TXRDYA-TXRDYD. A
logic 0 indicates a buffer ready status, i.e., at least one location is
empty and available in one of the TX channels (A-D). This pin goes to
a logic 1 when all four channels have no more empty locations in the
TX FIFO or THR. Individual channel TX status can be read by
examining individual internal registers via CS and A0-A4 pin
functions.
Power supply inputs.
RXRDY
38
-
54
O
TXA, TXB,
TXC, TXD
17, 19,
51, 53
8, 10,
39, 41
29, 32,
69, 72
O
TXRDY
39
-
55
O
V
CC
13, 30,
47, 64
35
4, 21,
35, 52
25
5, 25,
45, 65
50
I
XTAL1
I
Crystal or external clock input.
Functions as a crystal input or as
an external clock input. A crystal can be connected between this pin
and XTAL2 to form an internal oscillator circuit (see
Figure 7
).
Alternatively, an external clock can be connected to this pin to
provide custom data rates. (See
Section 6.10 “Programmable baud
rate generator”
.)
Output of the crystal oscillator or buffered clock.
(See also
XTAL1.) Crystal oscillator output or buffered clock output.
XTAL2
36
26
51
O
Table 2:
Pin description
…continued
Pin
PLCC68 LQFP64 LQFP80
Symbol
Type
Description
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