參數(shù)資料
型號(hào): SC16C554DIA68
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
中文描述: 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝: PLASTIC, MS-018, SOT-188-2, LCC-68
文件頁(yè)數(shù): 33/55頁(yè)
文件大?。?/td> 276K
代理商: SC16C554DIA68
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
33 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C554/554D provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
DSR
[1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
CTS
[1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
Table 20:
Bit
Modem Status Register bits description
…continued
Symbol
Description
Table 21:
Bit
7
Enhanced Feature Register bits description
Symbol
Description
EFR[7]
Auto CTS. Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
EFR[6]
Auto RTS. Automatic RTS may be used for hardware flow control by
enabling EFR[6]. When Auto RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return
to a logic 0 when data is unloaded below the next lower trigger level.
The state of this register bit changes with the status of the hardware flow
control. RTS functions normally when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic RTS flow control.
6
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