參數(shù)資料
型號(hào): SC16C550IN40
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: 0.600 INCH, MO-015, SOT-129-1, PLASTIC, DIP-40
文件頁(yè)數(shù): 30/52頁(yè)
文件大?。?/td> 639K
代理商: SC16C550IN40
Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
30 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C550 provides a temporary data register to store 8 bits of user information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
DSR
[1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
CTS
[1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
Table 20:
Bit
Modem Status Register bits description
…continued
Symbol
Description
Table 21:
Bit
7
Enhanced Feature Register bits description
Symbol
Description
EFR[7]
Automatic CTS flow control.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
6
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相關(guān)代理商/技術(shù)參數(shù)
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SC16C554B_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
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