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參數(shù)資料
| 型號： | SC16C550IN40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| 中文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, MO-015, SOT-129-1, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 639K |
| 代理商： | SC16C550IN40 |
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Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
10 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.1 Internal registers
The SC16C550 provides 15 internal registers for monitoring and control. These
registers are shown in
Table 3
. Twelve registers are similar to those already available
in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C550 offers an enhanced feature register set
(EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register
functions are more fully described in the following paragraphs.
[1]
[2]
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
“BF(HEX).
6.2 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached.
Table 3:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)
[1]
0
0
0
Receive Holding Register
0
0
1
0
1
0
Interrupt Status Register
0
1
1
1
0
0
1
0
1
Line Status Register
1
1
0
Modem Status Register
1
1
1
Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0
0
0
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)
[3]
0
1
0
Enhanced Feature Register
1
0
0
Xon1 word
1
0
1
Xon2 word
1
1
0
Xoff1 word
1
1
1
Xoff2 word
Internal registers decoding
A0
READ mode
A1
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C550IN40,112 | 功能描述:IC UART SINGLE W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| SC16C554 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554B_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554BIB64 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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