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| 型號： | SC16C2550IB48,128 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 4/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUART SOT313-2 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 特點(diǎn)： | 2 通道 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 其它名稱： | 935270020128 SC16C2550IB48-T SC16C2550IB48-T-ND |
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Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
12 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
the SC16C2550 compares two consecutive receive characters with two software ow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described ow control mechanisms, ow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overlling and ow control needs to be executed,
the SC16C2550 automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
6.6 Special feature software ow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software ow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
The SC16C2550 compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 7) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] dene the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the
SC16C2550 will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts
have lowest interrupt priority. A condition can exist where a higher priority interrupt
may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/RTS interrupt(s) be reected in the status
register. Servicing the interrupt without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C2550 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
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| SC16C2550IB48,157 | IC DUART SOT313-2 |
| SC16C2550IA44,518 | IC DUART SOT187-2 |
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| VI-B7N-IX-F1 | CONVERTER MOD DC/DC 18.5V 75W |
| SC16C2550BIN40,112 | IC UART DUAL W/FIFO 40-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2550IN40 | 制造商:PHILIP 功能描述: |
| SC16C2550IN40,112 | 功能描述:IC UART DUAL W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| SC16C2552 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
| SC16C2552B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs |
| SC16C2552BIA44 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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