參數(shù)資料
型號: SC16C2550IA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 11/46頁
文件大?。?/td> 603K
代理商: SC16C2550IA44
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
11 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.3 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
6.4 Hardware flow control
When automatic hardware flow control is enabled, the SC16C2550 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C2550 will continue to accept data until the receive FIFO is full.
6.5 Software flow control
When software flow control is enabled, the SC16C2550 compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C2550 will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C2550 will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C2550 will resume operation and
clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
Table 5:
Selected trigger level
(characters)
1
4
8
14
Flow control mechanism
INT pin activation
Negate RTS or
send Xoff
4
8
12
14
Assert RTS or
send Xon
1
4
8
10
1
4
8
14
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