參數(shù)資料
型號(hào): SC16C2550BIN40,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 30/31頁(yè)
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝: 9
特點(diǎn): 故障啟動(dòng)位檢測(cè)
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
其它名稱: 935274404112
SC16C2550BIN40
SC16C2550BIN40-ND
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
8 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
DSRA
-
37
41
39
I
Data Set Ready (active LOW). These inputs are associated
with individual UART channels, A through B. A logic 0 on this
pin indicates the modem or data set is powered-on and is ready
for data exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
DSRB
-
22
25
20
I
DTRA
-
33
37
34
O
Data Terminal Ready (active LOW). These outputs are
associated with individual UART channels, A through B.
A logic 0 on this pin indicates that the SC16C2550B is
powered-on and ready. This pin can be controlled via the
Modem Control Register. Writing a logic 1 to MCR[0] will set
the DTRn output to logic 0, enabling the modem. This pin will
be a logic 1 after writing a logic 0 to MCR[0] or after a reset.
This pin has no effect on the UART’s transmit or receive
operation.
DTRB
-
34
38
35
O
RIA
-
39
43
41
I
Ring Indicator (active LOW). These inputs are associated
with individual UART channels, A through B. A logic 0 on this
pin indicates the modem has received a ringing signal from the
telephone line. A logic 1 transition on this input pin will generate
an interrupt.
RIB
-
23
26
21
I
RTSA
23
32
36
33
O
Request to Send (active LOW). These outputs are associated
with individual UART channels, A through B. A logic 0 on the
RTSn pin indicates the transmitter has data ready and waiting
to send. Writing a logic 1 in the Modem Control Register
MCR[1] will set this pin to a logic 0, indicating data is available.
After a reset this pin will be set to a logic 1. This pin has no
effect on the UART’s transmit or receive operation.
RTSB
15
24
27
22
O
RXA
4
10
11
5
I
Receive data A, B. These inputs are associated with individual
serial channel data to the SC16C2550B receive input circuits,
A and B. The RXn signal will be a logic 1 during reset, idle (no
data) or when the transmitter is disabled. During the local
Loopback mode, the RXn input pin is disabled and TX data is
connected to the UART RX input, internally.
RXB
3
9
10
4
I
TXA
5
11
13
7
O
Transmit data A, B. These outputs are associated with
individual serial transmit channel data from the SC16C2550B.
The TXn signal will be a logic 1 during reset, idle (no data) or
when the transmitter is disabled. During the local Loopback
mode, the TXn output pin is disabled and TX data is internally
connected to the UART RX input.
TXB
6
12
14
8
O
n.c.
-
12, 24,
25, 37
-
not connected
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
HVQFN32 DIP40 PLCC44 LQFP48
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